Functional Coverage - Part 1

What does code coverage measure?

• How well your test bench exercises the functionality of the design

• How well your HDL code has been exercised by your test bench

• How efficiently your code is written

• How many bugs are in your design

Which of the following is automatically collected by the simulator?

• Functional coverage

• Performance coverage

• Code coverage

• Timing coverage

In functional coverage, what is required from the user?

• Nothing, it is fully automatic

• Define the functionality to be measured through coverage

• Write HDL code to collect coverage

• Measure simulation speed

Which of the following can SystemVerilog functional coverage constructs measure?

• Only variables

• Only transitions

• Variables, expressions, transitions, and cross coverage

• Only code execution

What is a covergroup in SystemVerilog?

• A module that generates signals

• A user-defined type that encapsulates a coverage model

• A function that runs test vectors

• A simulator option

How can a covergroup instance be created?

• Using the create() operator

• Using the new() operator

• Using the run() operator

• Using the init() operator

What is the purpose of bins in functional coverage?

• To store simulation logs

• To associate coverage points with sets of values, transitions, or cross-products

• To generate random test vectors

• To count HDL lines executed

How can coverage sampling be automatically triggered?

• Only manually in the testbench

• Using events and sequences

• By compiling the design

• By using code coverage

What happens if a coverpoint does not define any bins explicitly?

• Coverage cannot be collected

• SystemVerilog automatically creates state bins

• The testbench will fail

• No coverage is sampled

: How does SystemVerilog determine the number of automatic bins for a non-enum integral coverpoint?

• Always 10

• Equal to the variable size in bytes

• Minimum of 2^M and the value of auto_bin_max, where M is the number of bits needed

• Number of clock cycles in simulation