System Verilog MCQs on Data type

What is the default value of an uninitialized wire in System Verilog?

• 0

• 1

• x (unknown)

• z (high impedance)

Which of the following statements about wire is correct?

• Wire can store values between clock edges

• Wire represents combinational logic connections

• Wire can be assigned using always_ff blocks

• Wire supports procedural assignments

In System Verilog, what type of assignments can be made to reg variables?

• Only continuous assignments

• Only procedural assignments

• Both continuous and procedural assignments

• Neither continuous nor procedural assignments

What is the default size of a reg variable in SystemVerilog?

• 8 bits

• 16 bits

• 32 bits

• 1 bit

Which statement about the logic data type is correct?

• Logic can only be used in continuous assignments

• Logic can only be used in procedural assignments

• Logic can be used in both continuous and procedural assignments

• Logic is deprecated in SystemVerilog

What is the primary advantage of using logic over wire and reg?

• Logic is faster in simulation

• Logic uses less memory

• Logic unifies wire and reg functionality

• Logic supports more bit widths

What is the size of a shortint data type in SystemVerilog?

• 8 bits

• 16 bits

• 32 bits

• 64 bits

Which data type is 2-state (only 0 and 1 values)?

• logic

• reg

• bit

• wire

What is the precision of shortreal data type?

• 32-bit single precision

• 64-bit double precision

• 16-bit half precision

• 128-bit quad precision

Which statement about real data types is correct?

• Real variables can store X and Z values

• Real variables are 4-state variables

• Real variables are 2-state variables

• Real variables can be used in sensitivity lists