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Intro to VLSI

Total questions: 30

Worksheet time: 5mins

Name
Class
Date
1.

Electronics are characterized by

a)

low cost

b)

low weight and volume

c)

reliability

d)

all of the mentioned

2.

Speed power product is measured as the product of

a)

gate switching delay and gate power dissipation

b)

gate switching delay and gate power absorption

c)

gate switching delay and net gate power

d)

gate power dissipation and absorption

3.

nMOS devices are formed in

a)

p-type substrate of high doping level

b)

n-type substrate of low doping level

c)

p-type substrate of moderate doping level

d)

n-type substrate of high doping level

4.

Source and drain in nMOS device are isolated by

a)

a single diode

b)

two diodes

c)

three diodes

d)

four diodes

5.

In depletion mode, source and drain are connected by

a)

insulating channel

b)

conducting channel

c)

Vdd

d)

Vss

6.

The condition for non saturated region is

a)

Vds = Vgs – Vt

b)

Vgs lesser than Vt

c)

Vds lesser than Vgs – Vt

d)

Vds greater than Vgs – Vt

7.

In enhancement mode, device is in _________ condition

a)

conducting

b)

non conducting

c)

partially conducting

d)

insulating

8.

MOS transistor structure is

a)

symmetrical

b)

non symmetrical

c)

semi symmetrical

d)

pseudo symmetrical

9.

The condition for linear region is

a)

Vgs lesser than Vt

b)

Vgs greater than Vt

c)

Vds lesser than Vgs

d)

Vds greater than Vgs

10.

As source drain voltage increases, channel depth

a)

increases

b)

decreases

c)

logarithmically increases

d)

exponentially increses

11.

MOS transistors consists of

a)

semiconductor layer

b)

metal layer

c)

layer of silicon dioxide

d)

all of the mentioned

12.

In MOS transistors, _____ is used for their gate

a)

metal

b)

silicon dioxide

c)

polysilicon

d)

gallium

13.

The gate region consists of

a)

insulating layer

b)

conducting layer

c)

lower metal layer

d)

p type layer

14.

Electrical charge flows from

a)

source to drain

b)

drain to source

c)

source to ground

d)

source to gate

15.

Source in NMOS transistors is doped with ______ material

a)

n-type

b)

p-type

c)

n & p type

d)

none of the mentioned

16.

In N channel MOSFET which is the more negative of the elements?

a)

source

b)

gate

c)

drain

d)

source and drain

17.

Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch

a)

open, closed

b)

closed, open

c)

open, open

d)

close, close

18.

Overheating in device occurs due to less number of resistors per unit area.

a)

true

b)

false

19.

VLSI technology uses ________ to form integrated circuit

a)

transistors

b)

switches

c)

diodes

d)

buffers

20.

Medium scale integration has

a)

ten logic gates

b)

fifty logic gates

c)

hundred logic gates

d)

thousands logic gates

21.

______ architecture is used to design VLSI

a)

system on a device

b)

single open circuit

c)

system on a chip

d)

system on a circuit

22.

The design flow of VLSI system is

1. architecture design 2. market requirement 3. logic design 4. HDL coding

a)

2-1-3-4

b)

4-1-3-2

c)

3-2-1-4

d)

1-2-3-4

23.

Which provides higher integration density?

a)

switch transistor logic

b)

transistor buffer logic

c)

transistor transistor logic

d)

circuit level logic

24.

Physical and electrical specification is given in

a)

architectural design

b)

logic design

c)

system design

d)

functional design

25.

CMOS has

a)

high noise margin

b)

high packing density

c)

high power dissipation

d)

high complexity

26.

In CMOS fabrication, nMOS and pMOS are integrated in same substrate.

a)

true

b)

false

27.

P-well is created on

a)

p subtrate

b)

n substrate

c)

p & n substrate

d)

none of the mentioned

28.

What are the advantages of BiCMOS?

a)

higher gain

b)

high frequency characteristics

c)

better noise characteristics

d)

all of the mentioned

29.

In bipolar transistor, its quality can be improved by

a)

increasing collector resistance

b)

decreasing collector resistance

c)

collector resistance does not affect the quality

d)

decreasing gate resistance

30.

Why I am taking the VLSI design elective course

a)

Because this was the only course with vacancy

b)

Because I want to pioneer Malaysia's own Silicon Valley

c)

Because I foresee the bright future of VLSI and VLSI being the foundation of all tech related industry

d)

Because Dr Sharifah is so pretty