Font size
S
M
L
XL
Worksheets1.1.1. Structure and function of the processor
Total questions: 34
Worksheet time: 17mins
Name
Class
Date
1.
What does the Arithmetic and Logic unit do?
a)
completes all the arithmetical and logical operations.
b)
holds the address of the next instruction.
c)
Holds the address of a location that is to be read from or written to.
d)
Temporarily stores the data that has just been read from or the data needs to be written.
2.
What is the Control Unit?
a)
A part of the processor which directs operations inside the CPU.
b)
Small memory cells that operate at high speeds
c)
holds the address of the next instruction.
d)
Holds the address of a location that is to be read from or written to.
e)
Temporarily stores the data that has just been read from or the data needs to be written.
3.
What are registers?
a)
Small memory cells that operate at high speeds
b)
A part of the processor which directs operations inside the CPU.
c)
holds the address of the next instruction.
d)
Holds the address of a location that is to be read from or written to.
e)
Temporarily stores the data that has just been read from or the data needs to be written.
4.
Where do all the arithmetic, logic, or shift operations occur?
a)
They occur in registers
b)
PC
c)
MAR
d)
MDR
5.
What does the Program Counter (PC) do?
a)
holds the address of the next instruction.
b)
Holds the address of a location that is to be read from or written to.
c)
Temporarily stores the data that has just been read from or the data needs to be written.
d)
Small memory cells that operate at high speeds
e)
A part of the processor which directs operations inside the CPU.
6.
In which register do all calculations take place?
a)
The Accumulator.
b)
Cache
c)
PC
d)
MAR
e)
MDR
7.
What does the Memory Address Register do?
a)
Holds the address of a location that is to be read from or written to.
b)
Temporarily stores the data that has just been read from or the data needs to be written.
c)
Small memory cells that operate at high speeds
d)
A part of the processor which directs operations inside the CPU.
e)
holds the address of the next instruction.
8.
What does the Memory Data Register do?
a)
Temporarily stores the data that has just been read from or the data needs to be written.
b)
Small memory cells that operate at high speeds
c)
A part of the processor which directs operations inside the CPU.
d)
holds the address of the next instruction.
e)
Holds the address of a location that is to be read from or written to.
9.
What does the Current Instruction Register do?
a)
Holds the current instruction divided up into opcode and operand.
b)
Small memory cells that operate at high speeds
c)
A part of the processor which directs operations inside the CPU.
d)
holds the address of the next instruction.
e)
Holds the address of a location that is to be read from or written to.
10.
What is a Bus?
a)
A set of parallel wires connecting two or more components together.
b)
A bidirectional bus used to transport data and instructions between components
c)
The bi-directional bus used to transmit control signals between internal and external components
d)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
11.
What is the system bus?
a)
The collection of the data bus, address bus, and control bus
b)
A bidirectional bus used to transport data and instructions between components
c)
The bi-directional bus used to transmit control signals between internal and external components
d)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
12.
What is the width of a bus?
a)
The number of parallel wires it has.
b)
A bidirectional bus used to transport data and instructions between components
c)
The bi-directional bus used to transmit control signals between internal and external components
d)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
13.
What is the data bus?
a)
A bidirectional bus used to transport data and instructions between components
b)
The bi-directional bus used to transmit control signals between internal and external components
c)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
14.
What is the control bus?
a)
The bi-directional bus used to transmit control signals between internal and external components
b)
A bidirectional bus used to transport data and instructions between components
c)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
15.
What is the address bus used for?
a)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
b)
It doubles the number of addressable locations
c)
The bi-directional bus used to transmit control signals between internal and external components
d)
A bidirectional bus used to transport data and instructions between components
16.
What does adding a wire to the address bus do to the number of addressable locations?
a)
It doubles the number of addressable locations
b)
Used to transmit the memory address specifying where data is to be sent from or retrieved from.
c)
The bi-directional bus used to transmit control signals between internal and external components
d)
A bidirectional bus used to transport data and instructions between components
17.
What does the Bus Request indicate?
a)
indicates a device is requesting access to the data bus.
b)
Indicates the CPU has granted access to the data bus.
c)
Causes the data on the data bus to be written into the addressed location
d)
Causes the data from the addressed location to be placed onto the data bus
e)
Indicates that a device is requesting access to the CPU.
18.
What does Bus Grant indicate?
a)
Indicates the CPU has granted access to the data bus.
b)
Causes the data on the data bus to be written into the addressed location
c)
Causes the data from the addressed location to be placed onto the data bus
d)
Indicates that a device is requesting access to the CPU.
e)
indicates a device is requesting access to the data bus.
19.
What does memory write do?
a)
Causes the data on the data bus to be written into the addressed location
b)
Indicates that a device is requesting access to the CPU.
c)
indicates a device is requesting access to the data bus.
d)
Indicates the CPU has granted access to the data bus.
20.
What does memory read do?
a)
Causes the data from the addressed location to be placed onto the data bus
b)
Indicates that a device is requesting access to the CPU.
c)
indicates a device is requesting access to the data bus.
d)
Indicates the CPU has granted access to the data bus.
e)
Causes the data on the data bus to be written into the addressed location
21.
What does the interrupt request control signal indicate?
a)
Indicates that a device is requesting access to the CPU.
b)
indicates a device is requesting access to the data bus.
c)
indicates a device is requesting access to the data bus.
d)
Indicates the CPU has granted access to the data bus.
e)
Causes the data on the data bus to be written into the addressed location
22.
What is the clock control signal used for?
a)
It is used to synchronise instructions.
b)
The number of clock cycles completed per second.
c)
the CPU’s onboard memory which can be accessed a lot faster than main memory
d)
The process of completing the fetch, decode and execute of three separate files simultaneously
23.
What is Assembly Language?
a)
a programming language where mnemonics are used to represent instructions
b)
the address of where the operation is performed.
c)
used to determine the type of instruction and what hardware to use to execute it.
24.
What is opcode?
a)
used to determine the type of instruction and what hardware to use to execute it.
b)
the address of where the operation is performed.
c)
a programming language where mnemonics are used to represent instructions
25.
What is the operand?
a)
the address of where the operation is performed.
b)
used to determine the type of instruction and what hardware to use to execute it.
c)
a programming language where mnemonics are used to represent instructions
26.
What occurs during the fetch phase?
a)
The address from the PC is copied to the MAR,
b)
Instruction held at that address is copied to the MDR by the data bus, simultaneously the contents of the PC is increased by 1,
c)
The value of the MDR is copied to the CIR
d)
The contents of the CIR is split into operand and opcode.
e)
The opcode is executed on the data.
27.
What occurs during the decode phase?
a)
The contents of the CIR is split into operand and opcode.
b)
The address from the PC is copied to the MAR,
c)
Instruction held at that address is copied to the MDR by the data bus, simultaneously the contents of the PC is increased by 1,
d)
The value of the MDR is copied to the CIR
e)
The opcode is executed on the data.
28.
What occurs during the execute phase?
a)
The opcode is executed on the data.
b)
The address from the PC is copied to the MAR,
c)
Instruction held at that address is copied to the MDR by the data bus, simultaneously the contents of the PC is increased by 1,
d)
The value of the MDR is copied to the CIR
e)
The contents of the CIR is split into operand and opcode.
29.
What is the clock speed?
a)
The number of clock cycles completed per second.
b)
the CPU’s onboard memory which can be accessed a lot faster than main memory
c)
The process of completing the fetch, decode and execute of three separate files simultaneously
d)
It is used to synchronise instructions.
30.
What is cache memory?
a)
the CPU’s onboard memory which can be accessed a lot faster than main memory
b)
The number of clock cycles completed per second.
c)
The process of completing the fetch, decode and execute of three separate files simultaneously
d)
It is used to synchronise instructions.
31.
What is pipelining?
a)
The process of completing the fetch, decode and execute of three separate files simultaneously
b)
the CPU’s onboard memory which can be accessed a lot faster than main memory
c)
The number of clock cycles completed per second.
d)
It is used to synchronise instructions.
32.
What is Von Neumann architecture?
a)
Architecture in which there is a single shared memory and shared data bus for both data and instructions.
b)
Architecture in which there is two separate memory and data buses for data and instructions.
c)
Processing in which Von Neumann architecture is used for main memory. Cache uses Harvard architecture, divided into instruction cache and data cache
33.
What is Harvard architecture?
a)
Architecture in which there is two separate memory and data buses for data and instructions.
b)
Architecture in which there is a single shared memory and shared data bus for both data and instructions.
c)
Processing in which Von Neumann architecture is used for main memory. Cache uses Harvard architecture, divided into instruction cache and data cache
34.
What is contemporary processing?
a)
Processing in which Von Neumann architecture is used for main memory. Cache uses Harvard architecture, divided into instruction cache and data cache
b)
Architecture in which there is two separate memory and data buses for data and instructions.
c)
Architecture in which there is a single shared memory and shared data bus for both data and instructions.
Reset
