WorksheetsVLSI - Module 3
Total questions: 25
Worksheet time: 13mins
In Constant field model, the scaling factor of switching energy per gate would be
1/ β.α2
1/ α3
1/ α2
All of the mentioned
The gate delay is proportional to
Ron .Cg
Rs.Cds
Rd.Cgs
Ron.Cox
The dynamic component of power dissipation is given by:
P = I2.Rd
P = Vdd2/Rd
P = Eg.fo
All of the mentioned
The maximum operating frequency is scaled by
1/α2
β/α2
α2/β
1
The scaling factor similar to scaling factor of power speed product is:
Power dissipation per unit area
Switching Energy
Power dissipation per gate
All of the mentioned
For carry skip adder, the minimum total propogation delay can be obtained when m is
sqrt (nk1/k2)
sqrt (2nk1/k2)
sqrt (2k1/nk2)
sqrt (nk1k2/2)
The power dissipation per gate is scaled as:
1
1/ β.α2
α2/β
1/ β2
The scaling factor of Logic Level 1 in constant field model is:
1
1/β
1/α
α/β
logic is evaluated in the -------- phase of dynamic logic
precharge phase
evaluation phase
both
none
The saturation current is scaled by the factor of
1
1/α2
1/β
1/α
The bottom subfunction is called as
lower function
low cell
leaf cell
bottom cell
Some important features of system are
lower weight
lower volume
lower power dissipation
all of the mentioned
VLSI design is done in ____ approach
top-down
bottom-up
random
semi random
α is used for scaling
linear dimensions
vdd
oxide thickness
non linear
carry select adder is also called
manchester adder
carry skip adder
Conditional sum adder
carry propagate adder
Which design is preferred in n-bit adder?
many pass transistors in series
many pass transistors with suitable buffer
many pass transistors without suitable buffer
many pass transistors in parallel
When a polysilicon crosses a diffusion _____ will be formed
via
transistor
switch
short circuit
Which model is used for scaling?
constant electric scaling
constant voltage scaling
constant electric and voltage scaling
constant current model
p and g in the adder circuit represent the following respectively
xnor, and
xor, or
xnor, or
xor, and
Microelectronic technology cannot be characterized by
minimum feature size
power dissipation
production cost
designing cost
Approach used for design process are
circuit symbols
logic symbols
stick diagrams
all of the mentioned
one left shift is equal to ----- right shifts in a 4 bit barrel shifter
2
3
1
4
carry select adder improves the speed at the cost of extra
time
hardware
bits
none
For constant voltage model,
α = β
α = 1
α = 1/β
β = 1
Gate area can be given as
L/W
L * W
2L/W
L/2W
