wayground logo

Free Printable Worksheets

Font size

S
M
L
XL
Worksheets

VLSI - Module 3

Total questions: 25

Worksheet time: 13mins

Name
Class
Date
1.

In Constant field model, the scaling factor of switching energy per gate would be

a)

1/ β.α2

b)

1/ α3

c)

1/ α2

d)

All of the mentioned

2.

The gate delay is proportional to

a)

Ron .Cg

b)

Rs.Cds

c)

Rd.Cgs

d)

Ron.Cox

3.

The dynamic component of power dissipation is given by:

a)

P = I2.Rd

b)

P = Vdd2/Rd

c)

P = Eg.fo

d)

All of the mentioned

4.

The maximum operating frequency is scaled by

a)

1/α2

b)

β/α2

c)

α2/β

d)

1

5.

The scaling factor similar to scaling factor of power speed product is:

a)

Power dissipation per unit area

b)

Switching Energy

c)

Power dissipation per gate

d)

All of the mentioned

6.

For carry skip adder, the minimum total propogation delay can be obtained when m is

a)

sqrt (nk1/k2)

b)

sqrt (2nk1/k2)

c)

sqrt (2k1/nk2)

d)

sqrt (nk1k2/2)

7.

The power dissipation per gate is scaled as:

a)

1

b)

1/ β.α2

c)

α2/β

d)

1/ β2

8.

The scaling factor of Logic Level 1 in constant field model is:

a)

1

b)

1/β

c)

1/α

d)

α/β

9.

logic is evaluated in the -------- phase of dynamic logic

a)

precharge phase

b)

evaluation phase

c)

both

d)

none

10.

The saturation current is scaled by the factor of

a)

1

b)

1/α2

c)

1/β

d)

1/α

11.

The bottom subfunction is called as

a)

lower function

b)

low cell

c)

leaf cell

d)

bottom cell

12.

Some important features of system are

a)

lower weight

b)

lower volume

c)

lower power dissipation

d)

all of the mentioned

13.

VLSI design is done in ____ approach

a)

top-down

b)

bottom-up

c)

random

d)

semi random

14.

α is used for scaling

a)

linear dimensions

b)

vdd

c)

oxide thickness

d)

non linear

15.

carry select adder is also called

a)

manchester adder

b)

carry skip adder

c)

Conditional sum adder

d)

carry propagate adder

16.

Which design is preferred in n-bit adder?

a)

many pass transistors in series

b)

many pass transistors with suitable buffer

c)

many pass transistors without suitable buffer

d)

many pass transistors in parallel

17.

When a polysilicon crosses a diffusion _____ will be formed

a)

via

b)

transistor

c)

switch

d)

short circuit

18.

Which model is used for scaling?

a)

constant electric scaling

b)

constant voltage scaling

c)

constant electric and voltage scaling

d)

constant current model

19.

p and g in the adder circuit represent the following respectively

a)

xnor, and

b)

xor, or

c)

xnor, or

d)

xor, and

20.

Microelectronic technology cannot be characterized by

a)

minimum feature size

b)

power dissipation

c)

production cost

d)

designing cost

21.

Approach used for design process are

a)

circuit symbols

b)

logic symbols

c)

stick diagrams

d)

all of the mentioned

22.

one left shift is equal to ----- right shifts in a 4 bit barrel shifter

a)

2

b)

3

c)

1

d)

4

23.

carry select adder improves the speed at the cost of extra

a)

time

b)

hardware

c)

bits

d)

none

24.

For constant voltage model,

a)

α = β

b)

α = 1

c)

α = 1/β

d)

β = 1

25.

Gate area can be given as

a)

L/W

b)

L * W

c)

2L/W

d)

L/2W