In a multi-processor configuration two co-processors are connected to host 8086 processor. The instruction sets of the two co-processors

The feature of multi-microprocessor architecture is

The main objective in building the multimicroprocessor is

An interface between the user or an application program, and the system resources is

Zero address instruction format is used for

If no node having a copy of a cache block, this technique is known as

The straight-forward model used for the memory consistency, is called

______ have been developed specifically for pipelined systems.

The pipelining process is also called as ______

The fetch and execution cycles are interleaved with the help of ________

Each stage in pipelining should be completed within ___________ cycle.

If a unit completes its task before the allotted time period, then _______

To increase the speed of memory access in pipelining, we make use of _______

The periods of time when the unit is idle is called as _____

Pipelining increases the CPU instruction

The sum of the contents of the base register and the sign-extended offset is used as a memory address, the sum is known as

The process of letting an instruction move from the instruction decode stage into the execution stage of this pipeline is usually called

Situations that prevent the next instruction in the instruction stream, from executing during its designated clock cycle are known as

Hazards in pipelines can make it necessary to