WorksheetsUT- 2 (Quiz on verilog)
Total questions: 20
Worksheet time: 15mins
The input and output ports should be declared inside the ________
Module
Case
wire
None of the above
Which of the following loops are
supported by verilog?
if-else loop
for loop
while loop
All the above
The designers of Verilog wanted a language with syntax similar to the ________, which was already widely used in engineering software development
Pointer
python
C Programming
None of the above
VHDL uses an ___________declaration to
describe how a component or block should perform
Architectural
Behavioral
Module
None of the above
The "structural"style of programming in Verilog _________the designer to use sequential semantics to define the behavior of a hardware component or block
does not allow
allows
allows with condition
None of the above
One particular pitfall is the accidental production of ________ rather than D-type flip-flops as storage elements.
Integrated circuit
Latch (electronics)
NAND gate
Logic gate
Which level of abstraction level is available in Verilog but not in VHDL?
Behavioral level
Structural level
Dataflow level
Switch level
Which logic level is not supported by
verilog?
U
X
Z
None of the above
Variable and signal which will be updated first?
variable
signal
can't say
None of the above
Which of the following is true about parameters?
The default size of a parameter in most synthesizers is the size of an integer, 32 bits
Parameters enable Verilog code to be compatible with VHDL
Parameters cannot accept a default value
All of the above
Which of the following is a difference between a Function and a Task?
A Function can call another function; a Task cannot
A Function cannot call a task; a Task can call another task
A Function has one or more inputs; a Task has no inputs
A Function argument may be an output; a Task’s argument may only be an input
Which of the following is used for Verilog-based synthesis tools?
Intra-statement delay statements can be synthesized, but inter- statement delays cannot
Inter-statement delay statements can be synthesized, but intra- statement delays cannot
Initial values on wires are almost always ignored
Synthesized results are identical for “if” and “case” statements
Which directive is used to include
entire content of Verilog source Into another file?
'include
'ifdef
'indef
None
In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?
An error will be generated and the code cannot be synthesized
A warning message will be generated and the code will be synthesized but the resulting netlist will not provide the desired results
The synthesis tool will ignore the sensitivity list since all objects that are read as part of a procedural assignment statement are considered to be sensitive
There will be no effect on the design and pre-synthesis simulation will be consistent with post-synthesis simulation
The keyword @posedge means
Transition from 0 to 1,x or z
Transition from x to 1
Transition from z to 1,x
All the above
Verilog may be written at the
Behavioral level
Structural level
dataflow level
All the above
What is wrong with following piece of code
int a, b;
initial
begin
forever
begin
a=a+1; b=b+1;
end
end
Nothing wrong
incorrect a and b can overflow as it is incremented in an infinite loop
Simulation may not advance since forever doesn't have any timing control
A forever block cannot be used inside an initial block
Which of the following are true with respect to arrays?
Dynamic arrays are useful for contiguous collection of variables whose number keeps varying
Associative arrays can be used when size of an array is not known as it can be built as key/value pairs
Dynamic arrays can be re-sized after size is allocated once
All of above
Both tasks and functions can be coded in a way to take ________inputs and return _____ outputs in System Verilog
Multiple, Single
Single, Multiple
Multiple, Multiple
Single, Single
If a variable is not assigned in all possible executions of an always statement then
A don’t care is inferred
A latch is inferred
The variable is set to 0
The synthesis process will fail
