Worksheets22.07.2020 CAO 1
Total questions: 20
Worksheet time: 20mins
Name
Class
Date
1.
1. __________ is the bottleneck, when it comes computer performance.
a)
Memory access time
b)
Memory cycle time
c)
Delay
d)
Latency
2.
2.VLSI stands for ___________
a)
Very Large Scale Integration
b)
Very Large Stand-alone Integration
c)
Volatile Layer System Interface
d)
None of the mentioned
3.
3. Circuits that can hold their state as long as power is applied is _______
a)
Dynamic memory
b)
Static memory
c)
Register
d)
Cache
4.
4.The reason for the implementation of the cache memory is ________
a)
To increase the internal memory of the system
b)
The difference in speeds of operation of the processor and memory
c)
To reduce the memory access and cycle time
d)
All of the mentioned
5.
5.To increase the speed of memory access in pipelining, we make use of _______
a)
Special memory locations
b)
Special purpose registers
c)
Cache
d)
Buffers
6.
6.Computer memory which allows simultaneous read and write operation is
a)
ROM
b)
RAM
c)
EPROM
d)
EEPROM
7.
7.How is memory accessed in RISC architecture?
a)
load and store instruction
b)
opcode instruction
c)
memory instruction
d)
bus instruction
8.
8.Which of the following statements are true for von Neumann architecture?
a)
shared bus between the program memory and data memory
b)
separate bus between the program memory and data memory
c)
external bus for program memory and data memory
d)
external bus for data memory only
9.
9.The CISC stands for ___________
a)
Computer Instruction Set Compliment
b)
Complete Instruction Set Compliment
c)
Computer Indexed Set Components
d)
Complex Instruction set computer
10.
10.The computer architecture aimed at reducing the time of execution of instructions is ________
a)
CISC
b)
RISC
c)
ISA
d)
ANNA
11.
11. Pipe-lining is a unique feature of _______
a)
CISC
b)
RISC
c)
ISA
d)
ANNA
12.
12.Which of the architecture is power efficient?
a)
CISC
b)
RISC
c)
ISA
d)
ANNA
13.
13.ROM has the capability to perform _____________
a)
Write operation only
b)
Read operation only
c)
Both write and read operation
d)
Erase operation
14.
14.Since, ROM has the capability to read the information only then also it has been designed, why?
a)
For controlling purpose
b)
For loading purpose
c)
For booting purpose
d)
For erasing purpose
15.
15.Why are ROMs called non-volatile memory?
a)
They lose memory when power is removed
b)
They do not lose memory when power is removed
c)
They lose memory when power is supplied
d)
They do not lose memory when power is supplied
16.
16.How many types of RAMs are?
a)
2
b)
3
c)
4
d)
5
17.
17.The magnetic core memories have been replaced by semiconductor RAMs, why?
a)
Semiconductor RAMs are highly flexible
b)
Semiconductor RAMs have highest storing capacity
c)
Semiconductor RAMs are smaller in size
d)
All of the Mentioned
18.
18.Each stage in pipelining should be completed within ___________ cycle.
a)
1
b)
2
c)
3
d)
4
19.
19.While CPU is executing a program, an interrupt exists then it
a)
follows the next instruction in the program
b)
jumps to instruction in other registers
c)
breaks the normal sequence of execution of instructions
d)
stops executing the program
20.
20.If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a)
maskable interrupt
b)
nonmaskable interrupt
c)
vector interrupt
d)
nonvector inteerupt
100 %
