Worksheetscomputer Architecture - chapter 2
Total questions: 25
Worksheet time: 23mins
The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
When we use auto increment or auto decrement, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
The effective address of the following instruction is MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2]
d) 5*([R1]+[R2])
_____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
RTN stands for ___________
a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
The instruction, Add Loc,R1 in RTN is _______
a) Add SetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1]
Can you perform an addition on three operands simultaneously in ALU using Add instruction?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the mentioned
The instruction, Add R1,R2,R3 in RTN is _______
a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3]
c) R3=[R1]+[R2]
d) R3<-[R1]+[R2]
The two phases of executing an instruction are __________
a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
The Instruction fetch phase ends with _________
a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
While using the iterative construct (Branching) in execution _____________ instruction is used to check the condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
The condition flag Z is set to 1 to indicate _______
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
An 24 bit address generates an address space of ______ locations.
a) 1024
b) 4096
c) 248
d) 16,777,216
If a system is 64 bit machine, then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the mentioned
Computer use addressing mode techniques for
Giving programming versatility to the user by providing facilities as pointers to memory control for loop control
to reduce the number of bits in the field of instruction
specifying rules for interpreting address field of the instruction
all the above mentioned
The register used to store the flags is called as ______
Flag register
Status register
Test register
none
Which addressing mode execute its instructions within CPU without the necessity of reference memory for operands?
a. Implied Mode
b. Immediate Mode
c. Direct Mode
d. Register Mode
