WorksheetsAdvanced processor technologies
Total questions: 20
Worksheet time: 12mins
Which of the unit is not the part of the internal architecture of 80386?
(a) Central Processing Unit
(b) Memory Management Unit
(c) Bus Interface Unit
(d) None
How much virtual memory can be accessed by 80386 microprocessor?
(a) 1 MB
(b) 4 MB
(c) 4 GB
(d) 64 TB
A gigabyte represents…….
(a) 1 billion bytes
(b) 1000 kilobytes
(c) 230 bytes
(d) 1024 bytes
If the paging unit is enabled, then it converts linear address into
(a) effective address
(b) physical address
(c) segment base address
(d) none of the mentioned
The 80386 microprocessor is an enhanced version of (a)
80386 has a physical memory size of ___________
4GBytes
4MBytes
8GBytes
16GBytes
The 80386 also includes
32-bit extended registers and a 32-bit address and data bus.
16-bit extended registers and a 16-bit address and data bus.
16-bit extended registers and a 32-bit address and data bus.
32-bit extended registers and a 16-bit address and data bus.
The 80386 has a virtual memory with up to ______
64TBytes.
4GBytes.
4TBytes.
60TBytes.
The effective address (offset) is added with segment base address to calculate________
Linear address.
Local address
Both of the above
None of the above
The Pentium processor has two separate-------- caches on chip
8-kilobyte (KB)
4-kilobyte (KB)
5-kilobyte (KB)
None of the above
Pentium following (a) number of pipeline stages
___________Situations that prevent the next instruction in the instruction stream from executing during its designated clock cycles
Pipelining
Superscalar
Both of the above
None of the above
_________is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline.
Control hazard
Data hazard
structural hazard
None of the above
(a) second stage in instruction cycle
A=3+A
B=A*4
if these instruction execute in pipelining, which hazard can occur
Data hazard
Control hazard
Structural hazard
All of the above
This situation arises mainly when two instructions require a given hardware resource at the same time and hence for one of the instructions the pipeline needs to be stalled, known as
Data hazard
Control hazard
Structural hazard
All of the above
when one of the instructions is a branching instruction to some other memory location. Thus all the instruction fetched in the pipeline from consecutive memory locations are invalid now and need to removed(also called flushing of the pipeline). This is known as
(a)
Pentium has
A. Super scalar, pipelined architecture
B. Two separate caches
Only A
Both A and B
The real mode allows the microprocessor to address data in the first _________ of memory
1MByte
16MByte
4MByte
1GByte
Fetch, decode, execute, result writing performs simultaneously is known as
Cycle stealing
Pipelining
Both of the above
None of the above
