In which architecture do instructions and data each have their own bus?

In which architecture does a single control unit follow a linear fetch, decode and execute cycle?

In which architecture can the reading and writing of data be done at the same time as an instruction is being fetched?

In which architecture are instructions and data stored in a single, shared memory unit?

Which architecture processes just one instruction at a time?

Which architecture is used by RISC processors?

Which architecture uses registers to provide fast access to instructions and data?

A feature of contemporary architectures where a processor carries out a single instruction on multiple data at the same time.

A feature of contemporary architectures where a processor carries out a multiple instructions on multiple data at the same time.

Which instruction set requires less complex hardware?

Which instruction set might take more than one clock cycle to complete an instruction?

Which instruction set would require more lines of code to complete the same task?

With which instruction set does the compiler have to do more conversion work?

Which instruction set requires processor hardware and circuitry to be more complicated and therefore more expensive?

Which instruction set uses simple instructions which will be executed in a single clock cycle?

With which instruction set is more RAM needed to store the assembly instructions?

Which instruction set aims to complete a task in as few lines of assembly code as possible?

Which instruction set has hardware which has lower energy requirements?

Which instruction set could include a specific instruction for multiplying two numbers?

Which instruction set has become popular in portable devices such as tablet computers?