NEW
Font size
S
M
L
XL
WorksheetsEC8095_VLSI DESIGN_IAT2_PART A
Total questions: 30
Worksheet time: 30mins
Name
Class
Date
1.
1. A transmission gate is similar to a relay that can conduct in ________________ directions <br />by a control signal with almost any voltage potential(CO2) (B1)
a)
Single
b)
Both
c)
one
d)
None of the above
2.
2. The applications of the transmission gate includes ________________ (CO2) (B2)
a)
Electronic Switch
b)
Anolog multiplexers
c)
Logic circuits
d)
All the above0
3.
3. The monotonicity problem can be solved by placing a _____________ between dynamic gates. (CO2) (B2)
a)
static CMOS inverter
b)
AND gate
c)
XOR gate
d)
NAND gate
4.
4. What are the factors that causes a static power dissipation in CMOS circuits?(CO2) (B2)
a)
subthreshold current
b)
Tunneling and leakage current
c)
Contention current
d)
All the above0
5.
5. What are the factors that causes a dynamic power dissipation in CMOS circuits?(CO2) (B1)
a)
charging and discharging of load capacitance
b)
short circuit current
c)
both a and b
d)
None of the above
6.
6.Dual-rail domino gates accept both true and complementary ___________ (CO2) (B1)
a)
inputs
b)
inputs and outputs
c)
outputa
d)
None of the above
7.
7. To avoid Raced condition and delay in domino ngates, _____________are used. CO2) (B2)
a)
Inverters
b)
buffers
c)
np domino logic
d)
None of the above
8.
8. Cascade voltage switch logic is a differential type of logic circuit whereby ____________ inputs are required. (CO2) (B2)
a)
only true
b)
both true and complement
c)
only complement
d)
None of the above
9.
9. ___________ is feed back transistor of an inverter which is help to eliminate the static power dissipation in the inverter (CO2) (B2)
a)
limiter
b)
level restorer
c)
keeper
d)
None of the above
10.
10. Static CMOS and dynamic CMOS requires ____________ and ____________number of gates to implement a circuit respectively. (CO2) (B2)
a)
2N,N+1
b)
N+1,2N
c)
N+1,2N+1
d)
N+1,N+1
11.
11. Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input? (CO3) (B1)
a)
Combinational system
b)
sequential system
c)
both a & b
d)
None of the above
12.
12. The output of the sequential circuit depends on ___________________ (CO3) (B2)
a)
Present inputs
b)
Present and past inputs
c)
Past inputs alone
d)
None of the above
13.
13.The time required for an input data to settle _____ the triggering edge of clock is known as ‘Setup Time’. (CO3) (B2)
a)
before
b)
during
c)
after
d)
None of the above
14.
14. Hold time is defined as the time required for the data to ________ after the triggering edge of clock. (CO3) (B3)
a)
Increase
b)
Decrease
c)
Remain stable
d)
None of the above
15.
15.The latch is a _________________triggered device. (CO3) (B2)
a)
level
b)
edge
c)
both
d)
None of the above
16.
16. The FLIPFLOP is a _________________triggered device.(CO3) (B2)
a)
level
b)
edge
c)
both
d)
None of the above
17.
17. A latch stores when the clock__________<br />level is and is transparent<br />when the level is _________________________ (CO3) (B2)
a)
low , high
b)
high, low
c)
low, low
d)
high. High
18.
18. A FF stores when the clock _____________________ (CO3) (B2)
a)
stable
b)
falls
c)
rises
d)
None of the above
19.
19.The spatial variation in arrival time of a clock transition on an<br />integrated circuit is called _________________ (CO3) (B2)
a)
clock skew
b)
clock jitter
c)
glitches
d)
None of the above
20.
20. A temporal variation of the clock period at a given point on the chip is called __________________(CO3) (B2)
a)
clock skew
b)
clock jitter
c)
glitches
d)
None of the above
21.
21. _______________ is a popular design technique often used to accelerate the operation of the<br />data path in digital processors. (CO3) (B1)
a)
modeling
b)
dynamic logic
c)
domino logic
d)
Pipelining
22.
22. The major advantages of pipelining are to reduce____(CO3) (B2)
a)
glitching in complex logic networks
b)
getting lower energy due to operand isolation
c)
both a and b
d)
None of the above
23.
23.The positive edge triggered register based on master slave concept insensitive to clock overlap is called as____ (CO3) (B1)
a)
clocked CMOS or C2MOS register
b)
NORA CMOS register
c)
both a and b
d)
None of the above
24.
24. ____ is a logic circuit that combines C2MOS pipeline and NORA dynamic<br />logic function blocks. (CO3) (B1)
a)
NORA-CMOS
b)
clocked CMOS
c)
both a and b
d)
None of the above
25.
25. what are the functions of sense amplifirer? (CO3) (B1)
a)
Amplification & Delay reduction
b)
Power reduction
c)
Signal restoration
d)
all of the above
26.
26. When a CLK and CLK bar both are high for a short period of time (overlap period),both sampling pass transistors conduct and there is a direct path from the D input to a Q output. So output change at the rising edge of clock, which is undesired for a negative edge triggered register which is called ________ (CO3) (B1)
a)
Glitches
b)
Raced condition
c)
jitter
d)
None of the above
27.
27.Both SRAMs and DRAMs are ____ in nature. (CO3) (B1)
a)
volatile
b)
Non-volatile
c)
both a and b
d)
None of the above
28.
28.SRAMs provide high switching speed, good noise margin but require ____ than DRAMs.(CO3) (B1)
a)
high biasing
b)
more power
c)
large chip area
d)
all of the above
29.
29. ____ is a unknown state is neither 0 or 1.(CO3) (B1)
a)
metastability
b)
bistability
c)
both a and b
d)
None of the above
30.
30.Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points? (CO3) (B1)
a)
H-tree
b)
Balanced tree clock network
c)
Both a & b
d)
None of the above
Reset
