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Cache memory

Total questions: 15

Worksheet time: 6mins

Name
Class
Date
1.

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external.

a)

True

b)

False

2.

With write back updates are made only in the cache

a)

True

b)

False

3.

__________ refers to whether memory is internal or external to the computer.

a)

Hierarchy

b)

Tag

c)

Location

d)

Access

4.

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

a)

direct access

b)

random access

c)

sequential access

d)

associative

5.

individual blocks or records have a unique address based on physical location with __________

a)

associative

b)

physical access

c)

direct access

d)

sequential access

6.

Internal memory capacity is typically expressed in terms of _________

a)

hertz

b)

nanos

c)

bytes

d)

LOR

7.

The L1 cache is faster than the L3 cache

a)

True

b)

False

8.

__________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

a)

memory cycle time

b)

direct access

c)

transfer rate

d)

access time

9.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

a)

access time

b)

unit of transfer

c)

capacity

d)

memory ratio

10.

A line includes a _________ that identifies which particular block is currently being stored

a)

cache

b)

hit

c)

tag

d)

locality

11.

_________ is the simplest mapping technique and maps each block of main memory into only one possible

a)

Direct mapping

b)

Associative mapping

c)

Set associative mapping

d)

None of the above

12.

When using the __________ technique all write operations made to main memory are made to the cache as well.

a)

write back

b)

LRU

c)

write through

d)

unified cache

13.

__________ is the most effective replacement algorithm

a)

Random

b)

LFU

c)

LRU

d)

FIFO

14.

For set-associative mapping, the cache control logic interprets a memory address as __________

a)

3 fields

b)

2 fields

c)

1 field

d)

4 fields

15.

The most effective Replacement Algorithms for direct mapping

a)

LRU

b)

LFU

c)

FIFO

d)

No choice