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WorksheetsPipelining
Total questions: 18
Worksheet time: 54mins
A Pipelining is a series of stages in ______________
Asc/Desc order
one by one
Parallel
None of the Above
Advantage of Pipelining
Efficient use of resorces
Parallelism
Fastest Execution
All the above
Factors affecting the performance of Pipelining
Memory Conflicts
Branching
Interrupt
All the above
What is throughput in terms of instruction execution?
Rate of successful message delivery over network
Number of instructions executed per unit time
Disk data transfer rate
Units of time for an instruction to execute
Why is pipelining good?
Can execute multiple instruction stages in a clock cycle
Can skip all fetching stage
Can finish each instruction in one clock cycle
Can skip all ALU calculation
How many clock cycles do we save here using pipelining?
1
2
5
6
In which of the stages do we need ALU?
IF
EX
fetch, execute
ID/RR , MEM
In which of the stages do we need memory access?
Fetch, WB
Fetch, MEM
EX, Fetch
ID/RR, MEM
In which stage is PC incremented?
IF
EX
MEM
WB
What is a hazard in pipeline?
Overheating circuit
Conflict of data operations
Shortcircuit
Too many operations to execute
In pipelining the task which requires the least time is performed first.
a) True
b) False
Which of the following is an advantage of pipelining?
A. Instruction throughput increases.
B. Faster ALU can be designed when pipelining is used.
C. Pipelining increases the overall performance of the CPU.
D. All of the above
20. MAR stands for ___________
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register
Which of the following statements describes pipelining?
A small amount of memory located on the CPU.
Using multiple CPU cores to process multiple instructions simultaneously.
Allowing the CPU to switch between two threads while data is being fetched.
Using different parts of the CPU to perform different stages of multiple instructions simultaneously.
Pipelining means...
Running the fetch-decode-execute cycle more efficiently
Waiting for a full fetch-decode-execute cycle to complete before starting the next
Fetches the next instruction while the previous instruction is still decoding
CISC processors can run more efficiently
RISC processors can run more efficiently
CISC code can better utilise pipe-lining as the time needed for each operation can be predicted.
TRUE
FALSE
In a five stage pipelining , How many clock cycles are required to run 7 instruction.
9
10
11
12
Separate processes can overlap so that all parts of the CPU are active at any given time and this is called ?
parallelize
speculative execution
FLOPS
pipleline flush
