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Worksheets

CoQuizMod3

Total questions: 20

Worksheet time: 10mins

Name
Class
Date
1.

Pipelining is a ------------technique?

a)

Serial operation

b)

Parallel operation

c)

Scalar operation

d)

Superscalar operation

2.

Each stage of instruction should execute in ---------cycles?

a)

1

b)

2

c)

3

d)

4

3.

The initial stage for an instruction executing in pipelining is -----?

a)

Decode

b)

Execute

c)

Fetch

d)

Address generation.

4.

For a six-stage pipelining, the initial instruction requires-------cycle for execution?

a)

1 cycle

b)

3 cycle

c)

6 cycle

d)

7 cycle

5.

Parallelism can be achieved by-----------technique.

a)

Hardware

b)

Compiler

c)

Software

d)

All of the above

6.

To exploit Pipelining in computer architecture-----?

a)

A single processor is used.

b)

The double processor is used

c)

Multiple processors are used.

d)

None of the above.

7.

In a pipelined processor, the processing units for integers and floating point is-----?

a)

Same unit.

b)

Separate unit.

c)

No unit.

d)

Within each other.

8.

In---pipelining processor should pass the instructions through all the phases, regardless of the requirement of the requirements of instruction?

a)

Static

b)

Dynamic

c)

Complex Dynamic

d)

Both b and c

9.

In -----pipeline processor, instructions not only bypass the phases but also choose then out of order?

a)

Static

b)

Dynamic

c)

Complex Dynamic

d)

Both a and c.

10.

ARM processors are available in the form of -------- pipelining?

a)

3 stage

b)

5 stage

c)

Both a and b

d)

None of the above.

11.

The stages of 3 stage pipelining are----?

a)

Fetch, Decode, Execute

b)

Decode, Fetch, Execute

c)

Execute, Fetch, Decode

d)

Address generation, Fetch, Execute.

12.

---------instructions can cause a pipelining Hazard?

a)

Branch

b)

Interrupt

c)

Read after Write

d)

All of the above

13.

Throughput is calculated as----

a)

The number of instructions/ Total time to complete the instructions

b)

Total time to complete the instructions/number of instructions

c)

Speed of the processor/ Number of instructions

d)

The number of instructions/speed of the processor

14.

To hold the results of intermediate stages in pipelining --------are used?

a)

Caches

b)

Buffers

c)

Memory

d)

RAM units

15.

3 stage pipelining has ----- cycle latency?

a)

1

b)

2

c)

3

d)

4

16.

By using pipelining, the latency of the instructions---?

a)

Increases

b)

Remains the same

c)

Decreases

d)

It is unity

17.

In pipelining. each stage is given------time for the operation?

a)

Equal

b)

Different

c)

Infinite

d)

None of the above.

18.

In pipelining, instructions are executed----?

a)

Serially

b)

Parallel

c)

Concurrently

d)

None of the above.

19.

When the data operands are not available then it is called----?

a)

Deadlock

b)

Push

c)

Pop

d)

Data hazard

20.

In pipelining, which of the following operation is used to enhance the memory access speed?

a)

Registers

b)

Cache

c)

Stack

d)

Queue