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WorksheetsADC SEM2-QUIZ- PORTION SECOND
Total questions: 79
Worksheet time: 39mins
Name
Class
Date
1.
What is a multiplexer?
a)
It is a type of decoder which decodes several inputs and gives one output
b)
A multiplexer is a device which converts many signals into one
c)
It takes one input and results into many output
d)
It is a type of encoder which decodes several inputs and gives one output
2.
Multiplexers are also called__________
a)
Decoders
b)
encoders
c)
data selectors
d)
comparators
3.
If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a)
2
b)
m
c)
n
d)
2n
4.
4 to 1 MUX would have
a)
2 inputs
b)
3 inputd
c)
4 inputs
d)
5 inputs
5.
The enable input is also known as ___________
a)
Select input
b)
Decoded input
c)
Strobe
d)
Sink
6.
How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a)
3
b)
4
c)
2
d)
5
7.
In a multiplexer the output depends on its
a)
data inputs
b)
select inputs
c)
select outputs
d)
enable pins
8.
The two inputs MUX would have
a)
1 select line
b)
2 select line
c)
4 select line
d)
3 select line
9.
If enable input is high then the multiplexer is
a)
enable
b)
disable
c)
saturation
d)
High impedance
10.
Demultiplexers are also called
a)
Decoders
b)
encoders
c)
data distributors
d)
comparators
11.
In 1-to-4 demultiplexer ,how many select lines are required?
a)
2
b)
3
c)
4
d)
5
12.
The word demultiplexer means
a)
one into many
b)
many to one
c)
distributor
d)
one into many as well as distributor
13.
Which of the following circuits can be used as parallel to serial converter
a)
Multiplexer
b)
Demultiplexer
c)
Decoder
d)
digital counter
14.
Most demultiplexer facilitates which types of conversion?
a)
Decimal to hexadecimal
b)
Single input,multiple outputs
c)
AC to DC
d)
Odd parity to even parity
15.
Why is a demultiplexer called a data distributor?
a)
The input will be distributed to one of the outputs
b)
One of the inputs will be selected for the output
c)
The output will be distributed to one of the inputs
d)
Single input to Single Output
16.
Asynchronous counter is also known as __________ counter
a)
SYNCHRONOUS
b)
RIPPLE
c)
DELAY
d)
NONE OF THE ABOVE
17.
The counters in which the change in transition doesn’t depend upon the clock signal input is known as “____________
a)
UP COUNTER
b)
SYNCHRONOUS COUNTER
c)
Asynchronous counters”
d)
BISTABLE COUNTER
18.
Asynchronous sequential logic circuits ususlly performs operation in
a)
identical mode
b)
fundamental mode
c)
reserved mode
d)
reset mode
19.
In fundamental mode, the circuits is assumed to be in
a)
unstable state
b)
stable state
c)
reset state
d)
clear state
20.
In the asynchronous circuit,the changes occur with the changes of
a)
input
b)
output
c)
clock pulse
d)
Time
21.
The complexity of the asynchronous circuit is invovled in the timing problem of
a)
input
b)
outputs
c)
clock pulses
d)
feedback path
22.
The sequential circuits is also called
a)
combination circuits
b)
sequential circuits
c)
logic circuits
d)
complex circuits
23.
How many types of sequential circuits have?
a)
2
b)
5
c)
6
d)
7
24.
Sequential circuits are
a)
synhronous
b)
asynchronous
c)
signals
d)
both A and B
25.
Bidirectional counters, also known as ___________
a)
Up/Down counters
b)
UP COUNTER
c)
DOWN COUNTER
d)
NONE OF THE ABOVE
26.
UP-DOWN counter is a combination of ____________
a)
latches
b)
Flip flop
c)
Up counter
d)
Up counter& down counter
27.
UP-DOWN counter is also known as ___________
a)
Dual counter
b)
Multi counter
c)
Multimode counter
d)
Two Counter
28.
Once an up-/down-counter begins its count sequence, it
a)
Starts counting
b)
Can be reversed
c)
Can’t be reversed
d)
Can be altered
29.
In 4-bit up-down counter, how many flip-flops are required?
a)
2
b)
3
c)
4
d)
5
30.
In an UP-counter, each flip-flop is triggered by ___________
a)
The output of the next flip-flop
b)
The normal output of the preceding flip-flop
c)
The clock pulse of the previous flip-flop
d)
The inverted output of the preceding flip-flop
31.
In DOWN-counter, each flip-flop is triggered by ___________
a)
The output of the next flip-flop
b)
The normal output of the preceding flip-flop
c)
The clock pulse of the previous flip-flop
d)
The inverted output of the preceding flip-flop
32.
SIPO stands for _____________
a)
SERIAL OUT to PARALLEL IN
b)
SERIAL IN to PARALLEL IN
c)
SERIAL IN to PARALLEL OUT
d)
SERIAL OUT to PARALLEL OUT
33.
SISO stands for ____________
a)
SERIAL OUT to PARALLEL IN
b)
SERIAL IN to SERIAL OUT
c)
SERIAL IN to PARALLEL OUT
d)
SERIAL OUT to PARALLEL OUT
34.
PIPO stands for _____________
a)
SERIAL OUT to PARALLEL IN
b)
SERIAL IN to SERIAL OUT
c)
PARALLEL IN to PARALLEL OUT
d)
SERIAL OUT to PARALLEL OUT
35.
PISO stands for _____________
a)
SERIAL OUT to PARALLEL IN
b)
SERIAL IN to SERIAL OUT
c)
PARALLEL IN to PARALLEL OUT
d)
PARALLEL IN to SERIAL OUT
36.
Based on how binary information is entered or shifted out, shift registers are classified into _______ categories
a)
2
b)
3
c)
4
d)
5
37.
A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
a)
Tristate
b)
End around
c)
Universal
d)
Conversion
38.
How can parallel data be taken out of a shift register simultaneously?
a)
Use the Q output of the first FF
b)
Use the Q output of the last FF
c)
Tie all of the Q outputs together
d)
Shift Registers - Digital Circuits Questions and Answers - Sanfoundry
39.
What is meant by the parallel load of a shift register?
a)
All FFs are preset with data
b)
Each FF is loaded with data, one at a time
c)
Parallel shifting of data
d)
All FFs are set with data
40.
A parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________
a)
1110
b)
1
c)
1100
d)
1000
41.
Memory permits data to be stored and retrived at comparable speed is called
a)
R/W memory
b)
RAM memory
c)
ROM memory
d)
EPRAM memory
42.
Memory which is usually of random acess type is termed as
a)
main memory
b)
mass storage memory
c)
second memory
d)
flip flop
43.
SRAM stands for _________________
a)
STATIC RADIAL ACCESS MEMORY
b)
STATIC RANDOM ACCESS MEMORY
c)
STATE RANDOM ACCESS MEMORY
d)
NONE OF THE ABOVE
44.
ROM stands for
a)
READ ONLY MEMORY
b)
READY ONLY MEMORY
c)
RATE ON MEMORY
d)
RATE OFF MEMORY
45.
RAM stands for
a)
RADIAM ACCEPT MEMORY
b)
RADIOM ACCESS MEMORY
c)
A&B
d)
RANDOM ACCESS MEMORY
46.
Memory in which are data are available only in the same sequence in which the data were originally stored is
a)
sequential memory
b)
combinal memory
c)
stste memory
d)
flip flop
47.
Which of the following can easily convert to a non-volatile memory?
a)
SRAM
b)
DRAM
c)
DDR SRAM
d)
Asynchronous DRAM
48.
Which memory storage is widely used in PCs and Embedded Systems?
a)
SRAM
b)
DRAM
c)
Flash memory
d)
EEPROM
49.
Which of the following memory technology is highly denser?
a)
DRAM
b)
SRAM
c)
EPROM
d)
Flash memory
50.
Which is the storage element in DRAM
a)
Inductor
b)
capacitor
c)
resistor
d)
mosfet
51.
Which one of the following is a storage element in SRAM?
a)
Inductor
b)
capacitor
c)
transistor
d)
resistor
52.
Which of the following is more volatile?
a)
SRAM
b)
DRAM
c)
ROM
d)
RAM
53.
Flash memory devices are typically much faster at
a)
reading
b)
writing
c)
taking input signal
d)
generating output signal
54.
In NOR type flash memory, data is erased
a)
bitwise
b)
bytewise
c)
blockwise
d)
sentence wise
55.
In NOR type flash memory, each cell has one end connected to
a)
Source
b)
drain
c)
gate
d)
ground
56.
Flash memory is a non-volatile storage device in which data
a)
can be erased physically
b)
can be erased magnectically
c)
can be erased electrically
d)
cannot be erased
57.
Two types of digital circuit technology that use bipolar junction transistors are __________.
a)
TTL and ECL
b)
CMOS & NMOS
c)
NMOS & PMOS
d)
NONE OF THE ABOVE
58.
TTL stands for _______________
a)
TOGGLE TRANSISTOR LOGIC
b)
TOGGLE TOGGLE LOGIC
c)
TRANSISTOR TRANSISTOR LOGIC
d)
TRANSISTOR TOGGLE LOGIC
59.
CMOS stands for __________________
a)
COMPLIMENTARY METAL OXIDE SEMICONDUCTOR
b)
COMPLEX METAL OXIDE SEMICONDUCTOR
c)
COMPLIMENTARY MEASUREMENT OXIDE STATE
d)
NONE OF THE ABOVE
60.
what is meant by the fan-out of a logic gate-----------------
a)
the number of other gates that can be connected to the gates's output
b)
The physical distance between the voutput pins on the devices
c)
the number og other gates that can be connected to one of the gate's inputs
d)
the amount of cooling required by the gate
61.
The noise immunity ____________ with increase in noise margin
a)
decreases
b)
increases
c)
constant
d)
none of the mentioned
62.
what does Tphl indicates?
a)
delay time in going form high to low logic
b)
delay time in going form low to high logic
c)
delay time in going form high to high logic
d)
delay time in going form low to low logic
63.
An ADC inputs an analog electrical signal such as voltage or current and outputs ___________
a)
HEXADECIMAL NUMBER
b)
OCTAL NUMBER
c)
BINARY NUMBER
d)
DECIMAL NUMBER
64.
ADC stands for _________________
a)
ANALOG to DIGITAL CONVERTER
b)
AMPLITUDE DIGITAL CONVERTER
c)
ANGLE DATA CONVERTER
d)
NONE OF THE ABOVE
65.
ADC conversio involves
a)
quantization
b)
simulation
c)
summation
d)
substraction
66.
__________ is also called the parallel A/D converter
a)
SUCCESSIVE APPROXIMATION
b)
FLASH ADC
c)
R-2R LADDER
d)
BINARY WEIGHTED RESISTOR
67.
SAR stands for ________________
a)
FLASH ADC
b)
R-2R LADDER
c)
SUCCESSIVE APPROXIMATION REGISTER
d)
2R-4R LADDER
68.
The fastedt A/D converter is
a)
single slope ramp comparator A/D converter
b)
Dual slope integrator A/D converter
c)
Successive approximation A/D converter
d)
Counter type A/D converter
69.
Flash ADC consist of….converters
a)
2^n
b)
2^n-1
c)
2^n+1
d)
non of these
70.
flash ADC IS
a)
Serial ADC
b)
parallel ADC
c)
series -parallelADC
d)
SAR ADC
71.
The Ramp ADC uses a binary counter and digtal to analog converter to genertae a
a)
ramp equation
b)
ramp test waveform
c)
ramp input
d)
ramp output
72.
RAMP TYPE ADC is also known as the ___________
a)
stairstep-ramp
b)
SUCCESSIVE APPROXIMATION
c)
R-2R LADDER
d)
BINARY WEIGHTED RESISTOR
73.
DAC stands for ____________
a)
DATA TO AMPLITUDE CONVERTER
b)
DIGITAL to ANALOG converter
c)
DATA TO ANALOG CONVERTER
d)
NONE OF THE ABOVE
74.
A DAC, on the other hand, inputs a binary number and outputs an
a)
ANALOG CURRENT
b)
DIGITAL CURRENT
c)
DIGITAL VOLTAGE
d)
analog voltage or current signal
75.
A system that converts a digital signal into an analog signal is called
a)
ADC
b)
DAC
c)
AAC
d)
DDC
76.
What is the disdvantages of binary weighted type DAC?
a)
Rquire wide range of resistors
b)
High operating frequency
c)
high power consumption
d)
SLOW Switiching
77.
In a D-A converter with binary weighted resistor, a desired step size can be obtained by
a)
All of the mentioned
b)
selecting proper value of VFS
c)
Selecting proper value of R
d)
Selecting proper value of Rf
78.
In a binary ladder (R-2R),D/A converter ,the input resistance for each inpuy is
a)
R
b)
2R
c)
3R
d)
4R
79.
In ____________ type of DAC, the output voltage is the inverted sum of all the input voltages
a)
SUCCESSIVE APPROXIMATION
b)
R-2R LADDER
c)
2R-4R LADDER
d)
BINARY WEIGHTED RESISTOR
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