WorksheetsCArch Q2
Total questions: 10
Worksheet time: 30mins
Which of the following about I/O modules is FALSE?
The I/O module contains logic for the communication between the processor and the bus.
An I/O module recognizes the unique address for each peripheral it controls.
A set of I/O modules is a key component of a computer system.
I/O modules act as intermediaries between the processor and the I/O devices.
What is the function of the write command?
Causes the I/O module to test status conditions associated with its peripherals.
Causes the I/O module to activate a peripheral and tell it what to do.
Causes the I/O module to obtain an item of data from the peripheral and place it in
an internal buffer.
Causes the I/O module to take an item of data from the data bus and transmit it to the peripheral.
What is the function of the control logic in an external device?
Interprets the keyboard code and sends
the required electronic signals to the output device.
Temporarily holds the electronic signals generated by an input device.
Receives control signals from the I/O module and sends status signals to the I/O module.
Connects the external device to the I/O module.
What is the advantage of DMA (Direct Memory Access)?
Increases the number of clock cycles for each transfer.
Speeds up the read-write task without the involvement of the processor.
Offers low power consumption for the device.
Enables the device to use a higher-speed processor.
What is the FIRST step in the programmed I/O technique?
CPU writes the word into memory.
CPU reads the status of I/O module.
CPU reads the word from I/O module.
CPU issues the read command to I/O module.
Which of the following about RISC processors and instructions is FALSE?
Use a large amount of main memory.
Nearly all RISC instructions use simple register addressing.
The emphasis is on optimizing the instruction pipeline.
RISC processors are more responsive to interrupts.
Which of the following is NOT an advantage of pipelining?
Increases the overall instruction throughput.
Decreases instruction latency.
Increases the number of instructions executed simultaneously.
Increases the overall performance of the CPU.
Which of the following BEST describes data hazard?
Occurs when the pipeline must stall because certain conditions disallow continued execution.
When a second instruction tries to read data before the first instruction writes it.
A data transfer operation following an incomplete data transfer operation causes a resource stall.
Occurs when the pipeline makes a wrong decision on a branch prediction and therefore brings the wrong instruction into the pipeline.
What is a similarity between the RISC and CISC architectures?
Both refer to the category of the processor, or more accurately, the instruction set architecture.
Both require the same number of transistors on the chip.
Both have fixed format instructions.
Both execute one simple instruction per clock cycle.
What happens during the Decode instruction (DI) stage of pipelining?
Fetch each operand from memory.
Perform the indicated operation and store the result.
Read the next expected instruction into a buffer.
Determine the opcode and the operand specifiers.
