Worksheets2nd week
Total questions: 20
Worksheet time: 14mins
In Back-end design which timing violation has more priority? Why?
Setup, because setup timing already exists during Place stage
Hold, because hold violation is related to data path and no depends on clock; where setup can be eliminated by slowing the clock.
Setup, because setup related to clock and clock frequency cannot be adjusted
Hold, because setup can clean up easily by pushing clock
What is slack?
Hint: The time difference between _____ and _____ time ?
(a)
What is the routing components?
Logical connection and metal layers
metal layers and vias
Logical connection, vias and metal layers
One of the DRC violations is short. What does it mean by 'short'?
(a)
Routing blockage is one of the routing constraint. True or false?
True
False
From the NDR name specified in below command, can you guess what are the rules being applied to the net?
set_routing_rule [get_nets netA] -rule Track2X_Wide1X_Metal_With_Shield
Double spacing, single width and shielding
Single spacing, single width and shielding
Double spacing and single width
Double spacing, double width and shielding
What is the specific goal of Search and Repair by route_detail?
To reduce DRC
To reduce IR drop
To reduce EM violations
None of the above
Please list out one of the solution to fix Antenna violations
(a)
What is the purpose of tap cells? (Choose more than 1 answer)
Avoid latch up
Maintain VDD and VSS NWELL continuity
prevent DRC violations
prevent Antenna
How many types of Physical Verification we have? (Choose more than 1 answer)
CbTileANT
CbTileLVS
CbTileEDRC
CbTileDRC
CbTileMiniEDRC
Choose the correct answer for RED timing paths
Clock gating path
Asyn path
Clock path
Data path
What do we have for timing report header? (Choose more than 1 answer)
Startpoint
Endpoint
Slack
Path group and type
Which answer is NOT related to common path pessimism
Launch and capture clocks share a common path
Difference between the max delay and min delay of common clock path
STA have techniques to remove CM pessimism to achieve more accurate sign off result
Required time - data path time = clock common path
Multi cycle path is the timing path need take more than once clock cycle for the data to propagate from Starpoint to Endpoint.
True
False
Which color path is the shortest path?
RED
Yellow
Floorplan must be stable and lockdown. Which milestone should have this priority?
NLA
NLD
NLB
NLC
ECO
What is the things to check and make sure you can converge before you entering ECO milestone?
DRV
Timing
DRC
All answers
When you have pin terminal off track, what is the possible DRC violation you will see?
Width violation
Length violation
Spacing violation
Short
This DRC simply depicts the minimum area of the M4 layer (highlighted).
How will you going to fix this DRC? Please choose the correct answer
Extend the violated M4 shape
Change to higher metal layer
Add bigger via
Increase the layer width
Filler cells are cells with no logical functionality.
What if we missing filler cells, what violations we will get?
(Choose more than 1 answer)
Base violations
Density issue
Utilization issue
power rail issue
