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WorksheetsIHDL_Midterm Quiz
Total questions: 20
Worksheet time: 10mins
Turn off delay means, gate output transition to
0
1
z
x
In continuous assignment left hand side must be
net
reg
scalar or vetor net
scalar or vector reg
10 % 3 evaluates to
-1
1
0
x
For describing circuits like flip flops _____________ statement is used
always
assign
initial
forever
Which construct is used to execute loop fixed number of times
while
forever
for
none
Inout ports must always be
net
reg
trireg
none
RTL stands for _____________.
resistor‐transfer logic
register‐transistor logic
register‐transfer logic
none of these
Verilog is an
Case Insensitive
Case Sensitive
Can't say
The most appropriate modeling style to implement Traffic light controller will be
Dataflow
Structural
Behavioral
Switch
What is the basic unit of structural modeling?
Process
Component declaration
Component instantiation
Block
What do you mean by component instantiation?
To use the component
To describe external interface of the component
To declare the gate level components
To remove any component from the design
The structural model is similar to___________
Boolean relations of the circuit
Schematic block diagram of the circuit
Timing relations of the circuit
Components of the circuit
Which of the following is correct syntax for component declaration?
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END component_name;
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END COMPONENT;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END component_name;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END COMPONENT;
@posedge means
Transition from x to 1
Transition from 0 to 1, x or z
Transition from z to 1, x
Transition from 1 to 0
A loop statement is used where we needs to ________
Select one from many choices
Check a condition
Repeat the statements
Choose one from two cases
Loop is a ________ statement.
Concurrent
Sequential
Assignment
Functional
What is the use of FOR loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false
What is the use of WHILE loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false
Which of the following is correct syntax for WHILE LOOP?
label: WHILE LOOP specification IS sequential_statements;
END LOOP;
label: WHILE LOOP condition sequential_statements;
END LOOP label;
label: WHILE condition LOOP sequential_statements;
END LOOP label;
label: WHILE specification LOOP
sequential_statements; END LOOP;
The input and output ports should be declared inside the ________
Module
Case
wire
None of the above
