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Жұмыс парақтарыReview
Total сұрақ: 81
Worksheet time: 48mins
Arrange these types of memory in the order of fastest to slowest.
register-cache-ram-disk-tape
cache-register-disk-tape-ram
ram-cache-register-tape-disk
Yield decreases over time according to the learning curve.
True
False
Clock cycle is measured in Hertz.
True
False
This sequence of instruction: ADD(100h), (((300h))); MOV R1, (100h) causes this kind of data hazard.
Write After Write
Write After Read
None of the Above
Read After Write
A solution to data hazard where data paths allow data to be sent to the next instruction before it is written to its destination.
forwarding
none of the above
pipeline interlock
look-ahead method
stalling
One of these processor is NOT a RISC.
AMD Phenom II
ARM Cortex-A7
SPARC T4
PowerPC
Overclocking a computer requires a better cooling system to dissipate heat.
True
False
Which of the benchmarks mentioned above does Microsoft Office Word belongs?
Real Programs
MIPS
Toy Benchmarks
Kernels
MFLOPS
You are watching a certain movie from a VCD you have just borrowed from a friend. It always hangs up in a certain fight scene only. What causes this hang-up?
main memory
video card
Video Compact Disk
the whole machine
CDROM drive
0.09 micron is equivalent to 90 nanometer line width.
True
False
Among these choices. which is NOT a part of Dynamic Execution?
speculative execution
none of the above
all of the above
multiple branch prediction
dataflow analysis
External data width is about the number of bits that the CPU can process simultaneously.
True
False
It is an intel module that contains the CPU and an external L2 cache and it plugs into a socket on the motherboard which is more similar to a bus slot than an individual chip socket.
(a)
What does ZIF means?
(a)
An upgrade of performance by increasing its speedup enhanced is limited by
time spent in using the enhancement
performance of the old machine
performance of the new machine
none of the above
Among the choices, which is NOT a way to overclock a computer?
change system bus frequency
change both system bus frequency and CPU frequency multiplier
change the CPU frequency multiplier
change the memory frequency data transfer
The question of software availability and compatibility is part of which of these factors?
Functionality
Cost
None of the above
Performance
One of 3Dnow!'s problem is that it shares registers for integers and floating point.
True
False
Bandwidth is the amount of work done in a given time.
True
False
Time slicing is a method used to transfer data from one register to another within the CPU.
True
False
Size of a word specified in bits.
(a)
What Area of Development in processors does AMD PowerNow and AMD CoolCore Technology! developed?
(a)
Which statement best describes temporal locality of reference?
All of the above
None of the above
Item in database, stored in a single table will be accessed sequentially in most of the database query.
Reuse of data and instructions is already known after a program is recently used.
The maker of Sandy Bridge microarchitecture.
AMD
Apple
Samsung
ARM Holdings
Intel
Memory Function Complete is sent by the CPU control unit to Main Memory to complete a write or read operation
True
False
Performs all mathematical and logical operations within the CPU.
(a)
These are bunch of intelligent controller chips found on the motherboard, which controls the buses around the CPU.
(a)
The old execution time is 30 answers per minute. The enhancement is used 10% of the time. It is 20X faster than the original part. What is the new execution time for the machine to answer 30 questions?
0.1
20
33.85
27.15
1.105
It translates instructions from machine level code to the sequence of control signals that carry out the instruction.
(a)
The average selling price is measured by adding the component cost, direct cost and gross margin.
True
False
Hardware optimizations are can cause inconsistent results when using this benchmark.
Kernels
MIPS
Real Programs
MFLOPS
Synthetic Benchmarks
During the extraction of dies from a wafer, It was observed that there were 4 damaged dies for every 12 dies taken from the wafer. If a wafer costs P600, how much does each dies cost?
P300
P0.25
P150
P75
P0.33
The change in die yield is determined by
None of the above
number of holes in a die
All of the above
size of the wafer
A component of the computer system known as having the messiest organization.
Datapath
none of the above
Control
Input or Output
Memory
If the external clock works at 133 MHz and the CPU receives a signal every 4 ns, if the system employs clock doubling, at how fast would the internal clock be?
8 ns
266 MHz
2 ns
66.5 MHz
Thinner wires mean less power consumption.
True
False
Which of these is true?
The number of good dies is equal to the number of defective dies less than the number of dies in a wafer.
None of the above
Die yield is greater than the number of dies in a wafer.
All dies in a wafer less than the number of bad dies in the same wafer is the die yield.
The number of dies in a wafer less than the defective dies in the same wafer is the number of good dies.
Pipelining improves the time spent per instruction.
True
False
A register which holds the address of the next instruction to be executed.
none of the above
Memory Data Register
Memory Address Register
Arithmetic Logic Unit
Program Counter
External Clock Frequency refers to the speed of data transfer via the system bus.
True
False
MMX is introduced in 1995 in the Pentium processor.
True
False
A method where the processor time is shared to the other components in the machine.
Multitasking
Pipelining
none of the above
Time Slicing
A clock pulse is the interval between the start of a a cycle to the beginning of the next.
True
False
It is an implementation technique in processor design whereby multiple instructions are overlapped in execution.
(a)
Which of these best describes the learning curve?
As time passes, the quality of computer components increases.
The more the producer enhances the development of a device the better quality of this device is.
The longer the time it takes for a device to be manufactured the cheaper it becomes.
As time it passes, the lesser the cost of manufacturing of a certain device becomes.
Manufacturing cost is part of the direct cost.
A register which holds the data to be written to or just read from memory.
none of the above
Instruction Decoder
Arithmetic Logic Unit
Program Counter
Instruction Register
A hardware implementation is always faster than a software one.
True
False
Type of bus used by the Memory Address Register.
control bus
none of the above
data bus
address bus
Hyper-Threading is a technology used by Intel to simultaneously execute atmost 2 threads within a CPU core.
True
False
Multimedia applications require geometric transformation which deals with floating point computations.
True
False
Slot 1 cartridge is used to hold a K7 CPU chip from AMD.
True
False
The rarest phenomenon since writes occur late in the instruction cycle.
None of the Above
Write After Write
Read After Write
Write After Read
Which of these statements is/are false?
Technological advances change computer architecture design.
The simpler the development of a computer component the cheaper the component becomes
New designs of computer architecture improve low-end technology.
None of the above
Memory Function Complete signal is used by CPU to tell memory that if has finished its processing the data.
True
False
Spatial locality states that items whose addresses (or location) are near one another tend to be referenced close together in time.
True
False
A technique used by Intel in their new processors where it gradually increases the clock speed to match the increasing workload of the computer system.
(a)
A compiler could be used as a benchmark.
True
False
An architecture where there is a single path for data and instruction between the main memory and the CPU.
von neumann machine
harvard architecture
It is where the complete set of steps for each instruction is stored, ans is executed sequentially.
(a)
Electricity used for storage or warehouses of manufactured computer components is part of this cost.
None of the Above
Indirect or gross margin
Component Cost
Average Discount
Direct Cost
If Fetch (F) - 30 seconds; Decode (D) - 45 seconds; Operand Fetch (O) - 50 seconds; Execute (E) - 35 seconds; Store (S) - 30 seconds is what it takes for an instruction to complete its task, how many seconds will it take 3 instructions of this type to be executed sequentially?
435
570
460
50
190
Pipeline scheduling uses the compilers to modify the compiled code to avoid stalling.
True
False
Designing through software trends means taking notice on the rapidly occuring changes in the implementation technology.
True
False
It is a technique where more than one integer could be processed simultaneously.
(a)
What does EPIC stands for?
(a)
If we are about to upgrade a computer system's video card from 32 bit data transfer to 128 bit data transfer and the video card is used 3/4 of the time when it displays all graphical user interface (GUI) in this system, how much is the speedup enhanced?
32
4
0.75
128
0.25
The 2nd Instruction tries to read operand before the First Instruction writes it.
Write After Read
None of the Above
Read After Write
Write After Write
If Fetch (F) - 30 seconds; Decode (D) - 45 seconds; Operand Fetch (O) - 50 seconds; Execute (E) - 35 seconds; Store (S) - 30 seconds is what it takes for an instruction to complete its task, how many seconds will it take 5 instructions of this type to be executed in a pipeline with a depth of 3?(Note: the length of time adjusts to the maximum time spent in a set of segment within the pipelines)
570
435
460
190
38
Having a large word length means greater numeric precision.
True
False
Arrange these phases in the correct sequence of an instruction cycle.
Instruction Fetch-Instruction Decode-Operand Fetch-Execute-Result Store-Next Instruction
Next Instruction-Execute-Operand Fetch-Instruction Decode-Result Store-Instruction Fetch
Decode-Execute-Operand Fetch-Instruction Next Instruction-Result Store-Instruction Fetch
It is a type of socket designed for easy insertion of chips that have high density of pins.
Slot A
ZIF
Slot 2
Slot 1
What is the basic unit of CPU Speed?
Gigahertz
Hertz
Kilohertz
Megahertz
Suppose we have 5 instructions namely INSTRUC1, INSTRUC2, INSTRUC3, INSTRUC4, INSTRUC5 where INSTRUC2, INSTRUC3, and INSTRUC5 uses only the CPU registers for their operands and the remaining instructions uses the main memory for its operands. If each stage in an instruction spends 10 ns each (disregarding time to drain and time to fill), pipelining is used where the depth of the pipelines is 5, and DELAY STORE CYCLE is used to resolve structural hazards, how long will it take to complete the task of these 5 instructions?(Instructions is executed in the sequence as follows: INSTRUC1, INSTRUC2, INSTRUC3, INSTRUC4, INSTRUC5).
(a)
The zero flag register is asserted when the ALU operation result is zero.
True
False
Suppose we have 5 instructions namely INSTRUC1, INSTRUC2, INSTRUC3, INSTRUC4, INSTRUC5 where INSTRUC2, INSTRUC3, and INSTRUC5 uses only the CPU registers for their operands and the remaining instructions uses the main memory for its operands. If each stage in an instruction spends 10 ns each (disregarding time to drain and time to fill), pipelining is used where the depth of the pipelines is 5, and pipeline bubble is used to resolve structural hazards, how long will it take to complete the task of these 5 instructions?(Instructions is executed in the sequence as follows: INSTRUC1, INSTRUC2, INSTRUC3, INSTRUC4, INSTRUC5).
(a)
Executes each control signal in the sequence determined by the decoder.
Instruction Register
Arithmetic Logic Unit
Program Counter
none of the above
Memory Data Register
It is the portion of the pipeline execution where different phases execute at the same time.
(a)
CISC might use more registers than RISC.
True
False
Which of these best describes Moore's Law?
50% increase in performance of a processor expected in 1 year.
The processor's performance is doubled in 18 weeks.
The computer that costs $200 will become $64 in 1.5 years.
None of the above.
100% increase in processor's performance is expected in 18 months.
The system bus only facilitates data transfer between memory and CPU.
True
False
Unbalanced lengths of pipeline stages reduce speedup.
True
False
