deteriorates rapidly as a function of fan-in – quadratically in the worst case.

(a)  

Gates with a fan-in greater than WHAT should be avoided.

(a)  

Slope is a function of

(a)  

quadratic due to increasing resistance and capacitanceFan-in

(a)  

each additional fan-out gate adds two gate capacitances to CL

(a)  

as long as fan-out capacitance dominates

(a)  

Can reduce delay by more than 20%; decreasing gains as technology shrinks

(a)  

delay determined by time to discharge CL , C1 and C2

delay determined by time to discharge CL

(a)  

Or requires use of (a)   on the receiving end to restore the signal level (memory design)

Effort delay

(a)  

intrinsic delay

(a)  

Logical effort

(a)  

effective fanout

(a)  

is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

(a)  

increases with the gate complexity

(a)  

r has the smallest logical effort and intrinsic delay of all static CMOS gates

(a)  

a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current

(a)  

t is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current

(a)  

Every N-input logic gate requires 2N Transistors

(a)  

Transistors taken as (a)   controlled by gate

Requires extra inverter stage to realize non-inverting stage of complementary MOS

(a)  

With the exception of transient effects during switching period, output of the Gates assume the value of Boolean function implemented in circuit.

(a)  

VOH and VOL are at VDD and GND, respectively

(a)  

There never exists a direct path between VDD and VSS (GND) in steady-state mode.

(a)  

under the appropriate scaling conditions

(a)  

NMOS Logic Rules: HIGH Gate Voltage : switch is

(a)  

NMOS Logic Rules: LOW Gate Voltage

(a)  

NMOS Logic Rules HIGH Gate Voltage : switch

(a)  

NMOS Logic Rules LOW Gate Voltage : switch

(a)  

PMOS Logic Rules HIGH Gate Voltage : switch

(a)  

PMOS Logic RulesLOW Gate Voltage : switch

(a)  

PMOS Logic RulesHIGH Gate Voltage : switch

(a)  

PMOS Logic RulesLOW Gate Voltage : switch

(a)  

are Dual Logic Networks

(a)  

have the output connected either to a low impedance path to VDD or to the ground.

(a)  

Complementary Networks

(a)  

Transistor counts and clock frequencies have increased

(a)  

skyrocketed due to: o Transistor Scaling o Clock Frequencies o Chip Transistor Counts

(a)  

Power dissipation affects:

(a)  

Static Power

(a)  

Charging/ Discharging of Load Capacitor

(a)  

Also called Crowbar Current

(a)  

Saturation currents of PMOS and NMOS transistors which depends on

(a)  

Strong function of the ratio between input and output slopes

(a)  

Fast rise/fall times on input signal

(a)  

minimizing transistor size and reducing capacitance can reduce power dissipation.

(a)  

caused by switching transistors charging and discharging the load capacitor and also by short-circuit current when NMOS and PMOS devices are partially ON

(a)  

is caused by sub-threshold conduction, tunneling and reversebiased diode leakage c

(a)  

is due to static and dynamic power

(a)  

As transistor counts and clock frequencies increase, power dissipation

(a)