WorksheetsIHDL
Total questions: 192
Worksheet time: 2hrs 36mins
initial statement is
Synthesizable
Not Synthesizable
always construct is Synthesizable
True
False
#5 is Synthesizable
True
False
= and <= represent
Non-blocking and Blocking Assingment respectively
Blocking and Non-blocking Assingment respectively
Verilog is an
Case Insensitive
Case Sensitive
Can't say
Integer datatype is allocated ______ number of bits
16
32
64
8
reg [4:1] pwm will initialize variable of _______ bits
3
4
5
6
{,} is used to perform which operation
concat
Division
Exponent
Mod
The most appropriate modeling style to implement Traffic light controller will be
Dataflow
Structural
Behavioral
Switch
{1'b0, 2'b01, 3'b0} will result in
6'b 001001
6'b 001000
4'b 0010
4'b 0100
Shivani wish to implement 4:1 mux. Identify the errors in the line numbers of the code
4,16, 20,21
4, 17,20,22
4,16,20,22
4,17,20,21
Nitin Wish to implement Arithmetic unit capable of performing add, sub, mul and div operation. He written the following code identify the line numbers on which error exists.
8,15,21,23
8,16,21,23
10,15,22,23
10,16,22,23
Vishwesh wish to implement D-flipflop with clear input. So if clear is high he want the output to be zero else D-fliflop must follow Din. He written the following code identify the line numbers on which error exists.
9,13,16,17
11,13,14,16
14,16,17,18
9,14,16,17
Sumedh wish to implement 4-bit Synchronous Up/Down Counter. If reset state is high counter will reset to zero else depending on the mode pin state it will count up or Down. He decided that if Mode state is high then Counter will count up else vice versa.
4,8,12,16
5,10,16,21
10,13,16,22
8,10,12, 16
Gaurav wish to implement Half adder. He written the following code identify the line numbers on which error exists.
8,9,11,12
4,5,8,9
4,5,11,12
8,9,12,14
Modules written in verilog can represent a design
At the behavioral level
At the dataflow level
At the switch level
All of these
Operator which precedes the operand
Unary
Binary
Ternary
None
Which is legal negative number
4'd-3
6'-d3
-6d'3
None
What is the default value for reg data type
0
1
z
x
Turn off delay means, gate output transition to
0
1
z
x
What is system task to suspend simulation
$finish
$monitor
$display
$stop
Parameter value can be overridden at module instance by
Specparam
Defparam
Parameter
None
In continuous assignment left hand side must be
net
reg
scalar or vetor net
scalar or vector reg
10 % 3 evaluates to
-1
1
0
x
What are the possible values of == operator
0,1
0,x
1,x
0,1,x
What is the time period of clock #10 clock = ~clock
10
20
.05
.1
If x=4'b1100 then x<<2 is
4'b1000
4'b0000
4'b0011
4'b0110
If A=1'b1,B=2'b01,C=2'b00 then Y= {A,B[0],C[1]} equals
3'b110
3'b100
3'b101
3'b000
wait statement is
edge sensitive bit
level sensitive
both
none
<= is used in
Blocking
Non Blocking
Both
None
Asynchronous reset is
Clock dependent
Clock independent
Either
None
For describing circuits like flip flops _____________ statement is used
always
assign
initial
forever
Which construct is used to execute loop fixed number of times
while
forever
for
none
Inout ports must always be
net
reg
trireg
none
RTL stands for _____________.
resistor‐transfer logic
register‐transistor logic
register‐transfer logic
none of these
Electric Series circuit is equivalent to ______ gate.
NAND
OR
NOR
AND
Which of the following logic gate gives high output with all its inputs low
EXOR
OR
AND
NOR
Binary equivalent of decimal number 5 is ____
100
001
110
101
A demultiplexer has ________.
one input and one output
several inputs and several outputs
one data input and a number of selection inputs, and they have several outputs
several inputs and one output
A flip-flop has ________.
no stable states
two stable states
one stable state
none of the above
In positive logic, ________.
HIGH = 1, LOW = 0
only HIGHs are present
only LOWs are present
LOW = 1, HIGH = 0
A pulse has a period of 25 ms. Its frequency is ________.
40 Hz
400 Hz
4 Hz
50 Hz
VLSI technology uses ________ to form integrated circuit.
switches
diodes
buffers
transistors
______ architecture is used to design VLSI.
single open circuit
system on a device
system on a circuit
system on a chip
What is the design flow of VLSI system?
i. architecture design ii. market requirement iii. logic design iv. HDL coding
iv-i-iii-ii
iii-ii-i-iv
ii-i-iii-iv
ii-i-iv-iii
______ is used in logic design of VLSI.
LIFO
FILO
LILO
FIFO
Verilog is an
Case Insensitive
Case Sensitive
The full form of HDL is _________________
Hardware Description Language
High Descriptive Language
The Verilog HDL code starts with the keyword_________
always
module
Different types of modelling in Verilog HDL are _____
data, case and type
Gate, Logic and gates
Gate level, Data flow and Behavioral
In behavioral modeling the keyword used is _______
become
always
The symbol used for bitwise AND operation is _____
$
&
|
Which level of abstraction level is available in Verilog but not in VHDL?
Behavioral level
Structural level
Dataflow level
Switch level
How many number of 3 to 8 decoders are used to design 4 to 16 decoder?
2
5
8
4
RTL stands for _____________.
resistor‐transfer logic
register‐transfer logic
resistor‐transistor logic
register transistor logic
What is the basic unit of structural modeling?
Process
Component declaration
Component instantiation
Block
What do you mean by component instantiation?
To use the component
To describe external interface of the component
To declare the gate level components
To remove any component from the design
The structural model is similar to___________
Boolean relations of the circuit
Schematic block diagram of the circuit
Timing relations of the circuit
Components of the circuit
Which of the following is correct syntax for component declaration?
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END component_name;
COMPONENT component_name IS PORT ( port_mode : type port_name; port_mode : type port_name; ….); END COMPONENT;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END component_name;
COMPONENT component_name IS PORT ( port_name : mode type; port_name : mode type; ….); END COMPONENT;
Which construct is used to execute loop fixed number of times
repeat
while
forever
None
@posedge means
Transition from x to 1
Transition from 0 to 1, x or z
Transition from z to 1, x
Transition from 1 to 0
A loop statement is used where we needs to ________
Select one from many choices
Check a condition
Repeat the statements
Choose one from two cases
Loop is a ________ statement.
Concurrent
Sequential
Assignment
Functional
What is the use of FOR loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false
What is the use of WHILE loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false
Which of the following is correct syntax for WHILE LOOP?
label: WHILE LOOP specification IS sequential_statements;
END LOOP;
label: WHILE LOOP condition sequential_statements;
END LOOP label;
label: WHILE condition LOOP sequential_statements;
END LOOP label;
label: WHILE specification LOOP
sequential_statements; END LOOP;
What Is Sensitivity List?Which level simulates the algorithms that are used within the embedded systems?
gate level
circuit level
switch level
algorithmic level
Hardware Description language is another form of Programming Language.
TRUE
FALSE
Arithmetic operations with numbers in binary follow the same rules as for decimal numbers.
TRUE
FALSE
Digital systems are used only in communication and can’t be change according the specific needs.
TRUE
FALSE
Number system is a writing system for expressing numbers in mathematical notation to present numbers or a given sets using digits or other symbols in an inconsistent manner.
TRUE
FALSE
Arithmetic operations with numbers in binary follow the same rules as for decimal numbers.
TRUE
FALSE
Binary logic consists of binary variables and a set of logical operations.
TRUE
FALSE
OR operation is represented by a dot or by the absence of an operator.
TRUE
FALSE
A truth table is a table of all possible combinations of the variables, showing the relation between the values that the variables may take and the result of the operation.
TRUE
FALSE
Logic gates are electronic circuits that operate on one or more physical input signals to produce an output signal.
TRUE
FALSE
Verilog is a programming language used to describe a digital system that will be eventually implemented.
TRUE
FALSE
Give the Verilog Structure Template.
Give at least five testbench functional section.
Give the four abstraction layer and explain.
Explain how comment in Verilog function.
What are the three types of operators in Verilog and explain.
Explain how strings function.
Is a language that describes the hardware of digital systems in a textual form.
HDL
Verilog
VHDL
Logic Synthesis
A simulator interprets the HDL description and produces a readable output, such as a timing diagram, that predicts how the hardware will behave before its is actually fabricated.
HDL
Verilog
VHDL
Logic Synthesis tool
Is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits this was developed from an initiative by US. Dept. of Defense.
HDL
Verilog
VHDL
Logic Synthesis tool
It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using a HDL we can describe any digital hardware at any level. It was created by Phil Moorby and Prabhu Goel.
HDL
Verilog
VHDL
Logic Synthesis tool
The Verilog HDL code starts with the keyword_________
#
begin
always
module
The Verilog HDL testbench code starts with the keyword_________
#
begin
always
module
The Verilog HDL delay code starts with the keyword_________
#
begin
always
module
True or False: Verilog is case insensitive
True
False
Not sure
What Logic gate is shown in the figure below?
XOR
OR
AND
XNOR
What Logic gate is shown in the figure below?
XOR
OR
AND
XNOR
Verilog bitwise symbol of NOT
(a)
Verilog bitwise symbol of AND
(a)
Verilog bitwise symbol of OR
(a)
This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details.
(a)
The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gate-level logic diagram.
(a)
Logical negation will be done with the help of ____ gate
AND gate
OR gate
NOT gate
NAND gate
Logical addition will be done with the help of ____ gate
AND gate
OR gate
NOT gate
NAND gate
The behaviour of circuit will be explained in following modeling
Behaviour model
Data flow model
Structural model
Gate level model
The data processing of circuit will be explained in following modeling
Behaviour model
Data flow model
Structural model
Gate level model
The gates will be used to explain the circuit in following modeling
Behaviour model
Data flow model
Structural model
Gate level model
Logical multiplication will be done with the help of ____ gate
AND gate
OR gate
NOT gate
NAND gate
Half adder will be using following gates to the circuit
XOR & AND gate
XOR & OR gate
NOT & XOR gate
NAND & XOR gate
always will be used in program when we use following data type
wire
value set
register
integer
Verilog HDL is a case-sensitive language. All keywords are in _________.
lowercase
uppercase
either lower or uppercase
bold letters
Whitespace is ignored by Verilog except when it separates _________.
tokens
streams
comments
ASCII
Which is illegal in writing comments in verilog?
Embedding one-line comments in multiple-line comments
Embedding multiple-line comments in multiple-line comments
Embedding one-line comments after ;
all of the given
Which is a unary operator?
a = b && c;
a = ~b;
a = b & c;
a = b ? c : d;
Numbers that are specified without a <base format> specification are __________ numbers by default.
binary
decimal
octal
hexadecimal
For a 32-bit Windows, the specified number: 8'd255 has how many bits?
32
16
8
4
For a 32-bit Windows, the specified number: 255 has how many bits?
32
16
8
4
Default value of a net is ___.
0
1
x
z
Default value of a reg data type is ___.
0
1
x
z
Which of the following vector part selection is considered ILLEGAL for the given example:
wire [7:0] bus;
reg [0:31] virtual_add;
bus[5]
bus[1:0]
virtual_add[5:0]
virtual_add[0]
In this finite state machine how many states are there
1
2
3
4
Which state is the Starting State
Push
Un Locked
Locked
Coin
What do the arrows represent
States
Transformations
Inputs
Transitions
In this FSM how many inputs are there?
4
2
1
3
To move from the Locked state to Unlocked state what must the input be?
Push
Push Coin
Coin
Coin Push
When in the Locked state what happens when the input is Push
The state becomes Unlocked
Nothing happens
The machine refunds the coin
The machine unlocks and then locks
When Unlocked if the input is Push
The machine stays Unlocked
Nothing happens
The state changes to Locked
The state changes to coin
In this FSM which is the Accept State
S1
S2
0
1
Which is the Start State
1
S2
0
S1
When in State S2 if the input is 1
The machine will remain in state S2
The machine will change state to S1
The Machine will return to the Start State
The machine will return the value of 0
When the state is S2 if the input is 0
The machine will remain in the state S2
The machine will malfunction
0 is not a valid input
The machine will change state to S1
In this FSM the Accepted Input is
01
10
00
11
Starting at state S1 what state would input 'acd' change to
S1
S3
S4
S2
An input of 'ab' would result in state
S1
S2
S3
S4
At state S4 if the input is 'dbda' the machine is in state
S1
S2
S3
S4
In this FSM the Accept state is
S1
S2
S3
S4
Howm many inputs are there in this FSM
1
2
3
4
From the starting state is input 'abc' valid
YES
NO
What state will the machine rest in with an input of 'aabacda'
S4
S3
S2
S1
Final Question, what is the minimum accepted input of this Finite State Machine
acdb
abc
ac
ad
In this finite state machine how many states are there
1
2
3
4
Which state is the Starting State
Push
Un Locked
Locked
Coin
What do the arrows represent
States
Transformations
Inputs
Transitions
In this FSM how many inputs are there?
4
2
1
3
Which is the Start State
1
S2
0
S1
Howm many inputs are there in this FSM
1
2
3
4
There are ________ tuples in finite state machine.
4
5
6
Unlimited
Transition function of DFA maps.
Σ * 1 -> Σ
Q * Q -> Σ
Σ * Σ -> Q
Q * Σ -> Q
An NFA’s transition function returns
A Boolean value
A state
An edge
A set of states
Which is true for Dead State?
It cannot be reached anytime
There is no necessity of the state
If control enters no way to come out from the state
If control enters FA deads
The Tuples for NDFA
∑,Q,q0,F,δ
Q,q0,F,δ
Θ,Q,q0,F,δ
F,Q,Δ,q0, δ
Which of the following is a not a part of
5-tuple finite automata?
Input alphabet
Transition function
Initial State
output Alphabet
The DFA shown accepts the set of all strings over {0, 1} that
End with 00
End with 0
Begin either with 0 or 1
Contain the substring 00
{w | w ends with 010}
{w | w starts with 010}
{w | w contains 010 as a substring}
{w | w does not contain 010 as a substring}
Number of states require to accept string ends with 10.
3
2
1
5
When in State S2 if the input is 1
The machine will remain in state S2
The machine will change state to S1
The Machine will return to the Start State
The machine will return the value of 0
In this DFA the accepted Input is
01
10
00
11
Starting at state S1 what state would input 'acd' change to
S1
S3
S4
S2
An input of 'ab' would result in state
S1
S2
S3
S4
From the starting state is input 'abc' valid (accepted)?
YES
NO
What state will the machine rest in with an input of 'aabacda'?
S4
S3
S2
S1
There are ________ tuples in finite state machine.
4
5
6
7
Transition function maps.
Σ * Q -> Σ
Q * Q -> Σ
Σ * Σ -> Q
Q * Σ -> Q
Number of states require to accept string ends with 10.
3
2
1
can’t be represented.
Extended transition function is
Q * Σ* -> Q
Q * Σ -> Q
Q* * Σ* -> Σ
Q * Σ -> Σ
δ*(q,ya) is equivalent to .
δ((q,y),a)
δ(δ*(q,y),a)
δ(q,ya)
independent from δ notation
String X is accepted by finite automata if .
δ*(q,x) E A
δ(q,x) E A
δ*(Q0,x) E A
δ(Q0,x) E A
Languages of a automata is
If it is accepted by automata
If it halts
If automata touch final state in its life time
All language are language of automata
Language of finite automata is.
Type 0
Type 1
Type 2
Type 3
Finite automata requires minimum _______ number of stacks.
1
2
0
3
The basic limitation of finite automata is that
It can’t remember arbitrary large amount of information
It sometimes recognize grammar that are not regular
It sometimes fails to recognize regular grammar.
All of the mentioned
If NFA of 7 states is converted into DFA, maximum possible number of states for the DFA is ?
64
132
128
127
The sum of minimum and maximum number of final states for a DFA n states is equal to:
n+1
n
n-1
n+2
The minimum number of states required to recognize an octal number divisible by 3 are/is
1
3
5
7
Which of the following does not represents the given language?
Language: {0,01}
0+01
{0} U {01}
{0} U {0}{1}
{0} ^ {01}
Concatenation of R with Ф outputs
R
Ф
R.Ф
None
Which of the problems are unsolvable?
a) Halting problem
b) Boolean Satisfiability problem
c) Both (a) and (b)
d) None of the mentioned
Which of the following a turing machine does not consist of?
a) input tape
b) head
c) state register
d) none of the mentioned
A turing machine that is able to simulate other turing machines:
a) Nested Turing machines
b) Universal Turing machine
c) Counter machine
d) None of the mentioned
If d is not defined on the current state and the current tape symbol, then the machine
a) does not halts
b) halts
c) goes into loop forever
d) none of the mentioned
Which of the following are the models equivalent to Turing machine?
a) Multi tape turing machine
b) Multi track turing machine
c) Register machine
d) All of the mentioned
A turing machine operates over:
a) finite memory tape
b) infinite memory tape
c) depends on the algorithm
d) none of the mentioned
Which of the functions are not performed by the turing machine after reading a symbol?
a) writes the symbol
b) moves the tape one cell left/right
c) proceeds with next instruction or halts
d) none of the mentioned
Turing machine can be represented using the following tools:
a) Transition graph
b) Transition table
c) Queue and Input tape
d) All of the mentioned
Statement 1: Multitrack Turing machine.
Statement 2: Gamma is Cartesian product of a finite number of finite sets.
Which among the following is the correct option?
a) Statement 1 is the assertion and Statement 2 is the reason
b) Statement 1 is the reason and Statement 2 is the assertion
c) Statement 1 and Statement 2 are independent from each other
d) None of the mentioned
According to Chomsky hierarchy, which of the following is adopted by Recursively Ennumerable language?
a) Type 0
b) Type 1
c) Type 2
d) Type 3
Which of the following statements are false?
a) A multi track turing machine is a special kind of multi tape turing machine
b) 4-heads move independently along 4-tracks in standard 4-tape turing machine
c) In a n-track turing machine, n head reads and writes on all the tracks simultaneously.
d) All of the mentioned
A multitape turing machine is ________ powerful than a single tape turing machine.
a) more
b) less
c) equal
d) none of the mentioned
Which of the following is/are not an application of turing machine?
a) Language Recognization
b) Computers of functions on non negative numbers
c) Generating devices
d) None of the mentioned
Which of the following cannot be a possibility of a TM while it processes an input?
a) Enters accepting state
b) Enters non-accepting state
c) Enters infinite loop and never halts
d) None of the mentioned
Pick the odd one out.
a) Subroutines
b) Multiple tracks
c) Shifting over
d) Recursion
Which among the following is not true for 2-way infinte TM?
a) tape in both directions
b) Leftmost square not distinguished
c) Any computation that can be performed by 2-way infinite tape can also be performed by standard TM.
d) None of the mentioned
For the following language, an enumerator will print:
L={anbn|n>=0}
a) anbn
b) {ab, a2b2, a3b3, …}
c) {e, ab, a2b2, a3b3, …}
d) None of the mentioned
A man said to a lady, “Your mother’s husband’s sister is my aunt”. How is that lady related to that man?
(A) Daughter
(B) Grand-daughter
(C) Mother
(D) Sister
If X is brother of the son of Y’s son, how is X related to Y?
(A) Son
(B) Brother
(C) Cousin
(D) Grand-Son
Pointing to a photograph, a man said, “I have no brother or sister but that man’s father is my father’s son”. Whose photograph was it?
(A) His son’s
(B) His father's
(C) His nephew’s
(D) His own
