In fabrication ___________is the process of building wires to connect the devices.

Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

For a static CMOS, the output is high, then the state of the NMOS and PMOS are as follows

In high noise margin (NM_H), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.

In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?

In stick diagram, n and p transistors are separated by using ____________

In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.

The static PD for CMOS logic is maximum when input is at

------------------- can pass a logic 1 perfectly, but cannot pass a logic 0 perfectly

To ensure both read stability and writeability in SRAM; The nMOS pull down transistor must be sized _______ as compared to access transistors and pMOS transistor must be sized_______.

For a 1T DRAM the voltage swing on the bitline during read out is ____

Consider a memory is designed to store 512-bytes of data in a four-way fold. The number of address lines feed to a row decoder =_________ and column decoder =________ to access 8-bit data at a time.

If a designer wants to make nMOS 5X stronger than pMOS, then what sizes the designer end up having for Pseudo-nMOS inverter logic? Assume that the unit size inverter has .

The setup time is defined w.r.t positive edge of clock for _____ level Latch and for _____ edge-triggered flip-flop

To realize a negative-edge triggered flip-flop the master is built using _____ latch and the slave is built using _______ latch.

Determine the logic contamination delay in each clock cycle for 2 phase transparent latch with 10ps of non-overlapping between phases. Assume that the system is a causal system. The value of logic contamination delay is _______ps.

Given Clock skew 0ps; clock period 500ps;hold time 60ps; setup time 25ps; tCDQ 40ps; tCCQ 35ps; non-overlap 50ps

A 5 input NOR gate has a logical effort of _____ and parasitic delay of

______. Assume that the unit size inverter has 2/1

In a Hi-Skewed inverter, the value of βp is ________ βn.

Which mask is used for creating a body terminal of nMOS?

Which among the sequential elements have postponded output.

Which type of MOSFET exhibits no current at zero gate voltage?

Which model is used for scaling?

Which among the following is/are not suitable for in-system programming?

When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is: