WorksheetsSTA-2
Total questions: 10
Worksheet time: 8mins
What all information can be captured from Libraries? Tick all correct option
Cell Delay
Setup/Hold check value
RTL code for cell
Operating Condition
How to calculate Interconnect delay by using R and C Value?
Net delay = Inductance * Capacitance
Net delay = Resistance * capacitance
Net delay = Resistance * Inductance
None of these
Design constraints are needed for
Check functionality of design
check delay for cell and Net
Check Performance of Design
None of these
Wire-load model calculate delay based on
Cell area
Number of Fanouts
Number of Fanin
All of these
Which clock latency can be ignored after Place and Route?
Source Latency
Source and Network Latency
Network Latency
None of these
Which is required at input for IN->REGISTER path for accurate timing analysis?
Laod value
Driving Cell
Load Value and Driving cell
None of these
What is noise?
Unwanted signal
Required signal
Partially required signal
None of the above
Cross talk is due to
voltage source
current source
Coupling capacitance
uncoupled resistance
The language TCL means:
Test Command Language
Timing Command Langauge
None of the above
Tool Command Language
In Pre CTS the clock uncertainity includes
Clock Skew
Time margin
Clock jitter
All of the above
