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WorksheetsComputer Architecture
Total questions: 76
Worksheet time: 38mins
Reg No in full
The _________ controls the I/O devices and transfer of data to and from the primary storage.
LU
AU
ALU
CU
____________ enables the processor to access data quickly whenever they are needed.
CU
Cache
Memory
Register
The set of wires, which carry information in a controlled manner, is called
System bus
Public bus
Private bus
None of these
The ALU works on the instructions and data held in the _______________
Notebook
Registers
Copy Pad
I/O devices
The fastest memory in the computer system is _____________
ROM
RAM
Cache
None of these
A register that keeps track of the next instruction to be executed is called a _____________
Program Counter
Instruction Register
Accumulator
Data Register
A processor only operates on binary data, that is, data composed of 1s and 0s.
True
False
The address bus informs the CPU about the location of of the data residing in the memory.
The L2 cache is usually 64KB - 2MB in size.
_______________ is a large multilayered printed circuit board inside a computer that contains CPU,BIOS,ROM chip and the CMOS setup information.
Motherboard
RAM
ROM
Cache
The ___________ informs the CPU about the location of the data residing in the memory.
Data bus
Address bus
Cache
Control line
Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given latch delay is 10 ns. Calculate-
1:Pipeline cycle time
2: Non-pipeline execution time
90ns
110ns
100ns
120ns
A four stage pipeline has the stage delays as 150, 120, 160 and 140 ns respectively. Registers are used between the stages and have a delay of 5 ns each. Assuming constant clocking rate, the total time taken to process 1000 data items on the pipeline will be-
130.4 microseconds
165.5 microseconds
145 microseconds
158.4 microseconds
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. The speed up achieved in this pipelined processor is-
3.0
2.2
3.2
2.0
The stage delays in a 4 stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds.
The throughput increase of the pipeline is ___%.
31.33%
32.33%
33.33%
34.33%
Consider a pipelined processor with the following four stages-
IF : Instruction Fetch
ID : Instruction Decode and Operand Fetch
EX : Execute
WB : Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 ← R0 + R1
MUL R4, R3, R2 R4 ← R3 + R2
SUB R6, R5, R4 R6 ← R5 + R4
7
8
9
14
Which registers can interact with the secondary storage?
MAR
PC
IR
RO
During the execution of a program which gets initialized first?
MDR
IR
PC
MAR
Which of the register/s of the processor is/are connected to Memory Bus?
PC
MAR
IR
BOTH PC & MAR
The internal components of the processor are connected by (a)
The registers, ALU and the interconnection between them are collectively called as _____
PROCESS ROUTE
INFORMATION TRAIL
INFORMATION PATH
DATA PATH
(a) is used to store data in registers.
The ______ format is usually used to store data.
BCD
DECIMAL
HEXADECIMAL
OCTAL
The 8-bit encoding format used to store data in a computer is ______
ASCII
EBCDIC
ANCI
USCII
A source program is usually in (a)
Which memory device is generally made of semiconductors?
RAM
HARD DISK
FLOPPY DISK
CD DISK
The small extremely fast, RAM’s are called as _______
CACHE
HEAPS
ACCUMULATORS
STACKS
The ALU makes use of (a) to store the intermediate results.
The control unit controls other units by generating ___________
CONTROL SIGNALS
TIMING SIGNALS
TRANSFER SIGNALS
COMMAND SIGNALS
The Input devices can send information to the processor.
When the SIN status flag is set
When the data arrives regardless of the SIN flag
Either of the cases
Neither of the cases
The I/O interface required to connect the I/O device to the bus consists of (a)
The register which holds the address of the location to or from which data are to be transferred is called
Index Register
Instruction Register
Memory Address Register
Memory Data Register
The register used as a working area in CPU is
Program Counter
Instruction Register
Instruction Decoder
Accumualtor
The device which is used to connect a peripheral to bus is called . Control register B. Interface C. Communication protocol D. None of these
Control Register
Interface
Communication Protocol
None of these
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ?
Accumulator
Index Register
Instruction Decoder
Program Counter
The function of program counter (PC) holds
Temporary
Address for Memory
memory Operand
Address of Instruction
Which of the following is not a form of memory ?
Instruction Cache
Instruction Register
Instruction Opcode
Both (A) and (B)
A dynamic RAM consists of
6 Transistors
2 Transistors and 2 Capacitors
1 Transistor and 1 capacitor
None of These
Four memory chips of 16 x 4 size have their address bases connected together. The system will be of size
64 X 64
16 X 16
32 X 16
256 X 1
Microprocessor 8085 is the enhanced version of ......... with essentially the same construction set
4800
6800
8080
8088
The stack pointer in the microprocessor is a ______
16 bit register that points to stack memory locations
32 bit accumulator
memory location in the stack
flag regsiter used for the stack
This are the funtions of computer EXCEPT
data processing
data storage
data movement
data mining
CPU is stand for ______________ .
Central Processing Unit
Cerebral Palsy Unit
Control Processing Unit
Central Public Unit
What is the funtion of Arithmetic Logic Unit (ALU)?
Controls the operation of the CPU and hence the computer
Provides for communication
Performs the computer’s data processing functions
Provides storage internal to the CPU
A computer that stores data in terms of digits and proceeds in discrete steps.
Hybrid Computer
Analogue Computer
Digital Computer
Supercomputer
The register which holds the address of the location to or from which data are to be transferred is called
Index Register
Instruction Register
Memory Address Register
Memory Data Register
The register used as a working area in CPU is
Program Counter
Instruction Register
Instruction Decoder
Accumualtor
The device which is used to connect a peripheral to bus is called . Control register B. Interface C. Communication protocol D. None of these
Control Register
Interface
Communication Protocol
None of these
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ?
Accumulator
Index Register
Instruction Decoder
Program Counter
The function of program counter (PC) holds
Temporary
Address for Memory
memory Operand
Address of Instruction
Which of the following is not a form of memory ?
Instruction Cache
Instruction Register
Instruction Opcode
Both (A) and (B)
A dynamic RAM consists of
6 Transistors
2 Transistors and 2 Capacitors
1 Transistor and 1 capacitor
None of These
Four memory chips of 16 x 4 size have their address bases connected together. The system will be of size
64 X 64
16 X 16
32 X 16
256 X 1
Microprocessor 8085 is the enhanced version of ......... with essentially the same construction set
4800
6800
8080
8088
The stack pointer in the microprocessor is a ______
16 bit register that points to stack memory locations
32 bit accumulator
memory location in the stack
flag regsiter used for the stack
Bus ในยุคแรก
ISA
PCI
VLB
AGP
Interface สำหรับกราฟิกการ์ดในยุค 1960
VLB
AGP
AGP Pro
PCI
PCIe Launch ปีไหนคะ
2004
2007
2010
2017
ความเร็วของ PCIe 1.0 x1
250 MB/s
500 MB/s
985 MB/s
1.97 GB/s
Form Factor ของเมนบอร์ดที่นิยมใช้ในปัจจุบันคือ
ABC
AT
ATX
Micro ATX
The small extremely fast RAM is called as ___________.
Heap
Stack
Cache
Accumulator
Division by zero causes an ____________ interrupt.
implicit
internal
infinity
external
The ALU makes use of _________ to store the intermediate results.
Register
Accumulator
Stack
Heap
In _____________ addressing mode, the operand value is directly specified.
Relative
Direct
Indexed
Immediate
__________ is generally used to increase the apparent size of physical memory.
Secondary memory
Virtual memory
Hard Disks
Disks
MICR stands for ___________________________.
Magnetic Interface Character Resolution
Magnetic Ink Card Reader
Magnetic Ink Character Reading
Magnetic Ink Code Register
CISC stands for ______________________________________.
Complete Instruction Sequential Compilation
Computer Integrated Sequential Compiler
Complex Instruction Set Computer
Complex Instruction Sequential Compilation
In ______________ cache memory, the word is written into cache and main memory at the same time.
copy-back
write-through
copy-both
write-back
The address of the address of the operand is specified in _______________ addressing mode.
immediate
direct
indirect
relative
The register used to store the flags is called as ______________.
Flag register
Status register
Test register
Log register
In zero address instruction method, the operands are stored in __________.
registers
accumulators
push down stack
cache
To get the physical address from the logical address generated by the CPU, __________ is used.
MAR
MMU
TLB
Overlays
Interrupts form an important part of __________ systems.
Batch Processing
Multitasking
Real-time processing
Multi-user
In Register Transfer Language, ____________ is used to denote "Add the numbers in A and B and place the sum in A".
B ← A+B
A+B←A
A ← A+B
A+B → B
The CPU has two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged, _____________________ is needed.
a hardware interrupt
a software interrupt
either hardware or software interrupt
a non-privileged instruction
