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Worksheets1.1 - System Architecture - CPU [OCR] [GCSE]
Total questions: 10
Worksheet time: 5mins
Name
Class
Date
1.
Name the 3 operations of the CPU
a)
Fetch Decode Execute
b)
Find Read Do
c)
Execute Read Repeat
d)
Fetch Read Execute
2.
The Von Neumann architecture is when...
a)
Memory is divided into 3 parts, Fetch Decode and Execute
b)
Programs and Data are stored in the same memory
c)
Binary and Hex share the same memory
d)
Binary is used to store images
3.
The CPU is split into 2 main parts...
a)
ALU and Controller
b)
CPU and ALU
c)
Control Unit and ALU
d)
Control Unit and MDR
4.
The arithmatic Logic unit is where…
a)
Actual Calculations are carried out
b)
Data is processed
c)
Data is read to and written from
d)
RAM is emptied
5.
The control unit...
a)
Coordinates all the activities taking place in the CPU
b)
Carried out calculations
c)
Empties RAM
d)
Reads and Writes Data
6.
What is the purpose of the MAR
a)
Holds the data fetched from memory
b)
Holds the result of any equations carried out by the ALU
c)
Holds the memory address of the next instruction to be fetched from memory
d)
Holds the address of the instruction being fetched
7.
What is the purpose of the MDR
a)
Holds the data fetched from memory
b)
Holds the result of any equations carried out by the ALU
c)
Holds the memory address of the next instruction to be fetched from memory
d)
Holds the address of the instruction being fetched
8.
What is the purpose of the Accumulator
a)
Holds the data fetched from memory
b)
Holds the result of any equations carried out by the ALU
c)
Holds the memory address of the next instruction to be fetched from memory
d)
Holds the address of the instruction being fetched
9.
What is the purpose of the Program
a)
Holds the data fetched from memory
b)
Holds the result of any equations carried out by the ALU
c)
Holds the memory address of the next instruction to be fetched from memory
d)
Holds the address of the instruction being fetched
10.
What is a register on the CPU
a)
A super Fast Memory location
b)
A piece of RAM
c)
Software in control of input and Output
d)
Hardware in control of Input and output
Reset
