WorksheetsAssesment:One-Week ATAL FDP On “Recent Advancements in VLSI
Total questions: 25
Worksheet time: 38mins
1. In IC fabrication process, at what temperature soft bake process is performed and select its purpose
300C to 600C and to apply extra photoresist
900C to 1000C and to remove the residual solvents of the photoresist
1800C to 2000C and to perform lithography
1200C to 1600C and to perform annealing
2. Select appropriate dynamic power expression.
a. PD = CL VDD2 fclk
a. PD = RL VDD fclk
a. PD = CL VDD2 fclk2
a. PD = RL VDD2 fclk
3. Issue arises out of Clock Domain Crossing (CDC) check
Data Loss
Glitches
Both a&b
LVS error
4.Power dissipation is directly related to.
Frequency of operation
Square of VDD
Both a & b
Amplitude of input signal
5.Dynamic power in VLSI circuits depends on the following parameters
Supply voltage
Bit transition
Time to market
Both a & b
6.Static power dissipation can be optimized by employing
Capacitance compensation technique
Clock gating technique
Pipelining technique
Parallel architecture technique
7.Main parameter to be considered for reduction of power dissipation
Static power dissipation
Dynamic power dissipation
Leakage power dissipation
Both b & c
8.Select proper sequence for RTL design
Micro Architecture, Specifications, RTL design, Synthesis, Functional simulation, Timing verification, Device programming
Specifications, Micro Architecture, RTL design, Functional simulation, Synthesis, Timing Verification, Device programming
RTL design, Specifications, Micro Architecture, synthesis, timing verification, Device programming, Functional simulation
Functional simulation, Specifications, Micro Architecture, RTL design, Synthesis, Timing Verification, Device programming
9.Digital system design can be done using the following minimum number of logic blocks
Encoders & Decoders
Multiplexers & demultiplexers
Multiplexers & D-Flip Flops
Demultiplexers & T-Flip flops
10.Which of the following is true for good coding practice
Use blocking statements for combinational circuits
Use non-blocking statements for sequential circuits
Both a & b
Use null statements
11.CDC (Clock Domain crossing Check) and LEC (Logic equivalence Check) are performed tools using
Mentor Graphics and Cadence
Spyglass and Cadence
Symica DE and Xilinx
These checks must be done physically
12.Cost Effective parameter in IC fabrication
Oxidation
Lithography
Annealing
Photoresist
13.To improve delay performance, one of the following statements is used
Assign statement
Always block
Case statement
If statement
14.Which of the following is self-aligned technology process
All the source, drain and gate formed at a time
Source and drain formed first; gate is formed later
Gate is formed first; source and drain are formed later
Gate, source, and drain are formed one after the other
15.Select dry etch and wet etch techniques for silicon nitride etching
Plasma ashing(PA) and Buffered Oxide Etch(BOE)
Buffered Oxide Etch(BOE) and Plasma ashing(PA)
Buffered Hydrofluoric acid(BHF) and Buffered Oxide Etch(BOE)
Silicon nitride cannot be etched using above techniques
16.Profilometry is used for one of the following
To apply photoresist
To perform lithography
To estimate the top film thickness
To calculate area of metal contact
17.Select appropriate device modeling methods mentioned below
Black Box modeling
Subcircuit modeling
Compact modeling
All a&b&c
18.Which of the following is the package density for VLSI technology
10 gates to 100 gates
10000 gates and above
1000 gates to 10000 gates
100 gates to 1000 gates
19.Select appropriate acronym for “ASIC”.
Asynchronous Synchronous Integrated circuit
Application Simulated Integrated Circuit
Application Specific Integrated Circuit
Automatic Synthesizable Integrated Circuit
20.Which of the following is false related to FPGA design
Short development time
Low NRE costs
The design size is limited
Supports complex design
21.Select appropriate expression for FIR filter
y(n) =k=0∑Nh(k)x(n−k)
y(n) =k=0∑N−1h(k)x(n−k)
y(n) =k=0∑Nh(n−k)x(n)
y(n) =k=0∑N−1h(n−1)x(n−k)
22.Select appropriate acronym for “BGR”
Bandwith to Gain Ratio
Band Gap Reference
Base Gain Reference
Balanced Gate Reference
23.Which one of the following is sub circuit in Analog to digital conversion
Store and halt circuit
Sample and hold circuit
Smoothing circuit
Synchronizing circuit
24.Which of the following is not a functional block of Phase Locked Loop
Loop filter
Voltage Controlled Oscillator
RF amplifier
Phase Detector
25.In CMOS fabrication technology, Photoresist is exposed to
Fluorescent light
Ultraviolet light
InfraRed light
Visible light
