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VLSI Chip Design Quiz

Total questions: 20

Worksheet time: 13mins

Name
Class
Date
1.

Rifts are used for smooth flow through buses.

4 lines
2.

CMOS inverter has ______ output impedance.

a)

low

b)

high

c)

very high

d)

none of the mentioned

3.

In inverter circuit ________ transistors is used as load

a)

enhancement mode

b)

depletion mode

c)

all of the mentioned

d)

none of the mentioned

4.

In CMOS NAND gate, p transistors are connected in

a)

series

b)

parallel

c)

cascade

d)

random

5.

Schottky barrier is created due to the difference in

a)

voltages

b)

thickness

c)

work function

d)

density

6.

If both the transistors are in saturation, then they act as ________

a)

current source

b)

voltage source

c)

divider

d)

buffer

7.

In basic inverter circuit _____________ is connected to ground.

a)

source

b)

gates

c)

drain

d)

resistance

8.

Inverters are essential for ________

a)

NAND gates

b)

NOR gates

c)

sequential circuits

d)

all of the mentioned

9.

Simulator converts circuit information to

a)

design plan

b)

does verification

c)

set of equations

d)

floor plan

10.

If βn = βp, then Vin is equal to ________

a)

Vdd

b)

Vss

c)

2Vdd

d)

0.5Vdd

11.

Gallium arsenide crystals are grown from

a)

boron oxide

b)

silicon oxide

c)

silicon nitride

d)

boron nitride

12.

The accuracy of simulation depends on accuracy of

a)

fabrication house parameters

b)

electrical parameters

c)

active parameters

d)

functional parameters

13.

If n-transistor conducts and has large voltage between source and drain, then it is said to be in _____ region.

a)

linear

b)

saturation

c)

non saturation

d)

cut-off

14.

Which gate is faster?

a)

AND

b)

NAND

c)

NOR

d)

OR

15.

Which gives the main electrical behaviour of various parts of the circuit?

a)

circuit simulator

b)

timing simulator

c)

logic level simulator

d)

functional simulator

16.

CMOS inverter has ______ regions of operation.

a)

three

b)

four

c)

two

d)

five

17.

Reduction in power dissipation can be brought by

a)

increasing transistor area

b)

decreasing transistor area

c)

increasing transistor feature size

d)

decreasing transistor feature size

18.

What is the ratio of Zp.u/Zp.d?

a)

1/4

b)

4/1

c)

1/2

d)

2/1

19.

The area of CMOS inverter is proportional to

a)

area of n device

b)

area of p device

c)

total area of n and p device

d)

square of minimum feature size

20.

Which occupies lesser area?

a)

Vdd pads

b)

Vss pads

c)

input pads

d)

output pads