WorksheetsTRUE FALSE QUESTION
Total questions: 300
Worksheet time: 5hrs 0mins
Name
Class
Date
1.
- There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer".
(T/F)
a)
T
b)
F
2.
- The variety of computer products is exhibited only in cost.
(T/F)
a)
T
b)
F
3.
- Computer organization refers to attributes of a system visible to the programmer.
(T/F)
a)
T
b)
F
4.
- Changes in computer technology are finally slowing down.
(T/F)
a)
T
b)
F
5.
- The textbook for this course is about the structure and function of computers.
(T/F)
a)
T
b)
F
6.
- The number of bits used to represent various data types is an example of an architectural attribute.
(T/F)
a)
T
b)
F
7.
- Interfaces between the computer and peripherals is an example of an organizational attribute.
(T/F)
a)
T
b)
F
8.
- Historically the distinction between architecture and organization has not been an important one.
(T/F)
a)
T
b)
F
9.
- A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology.
(T/F)
a)
T
b)
F
10.
- A microcomputer architecture and organization relationship is not very close.
(T/F)
a)
T
b)
F
11.
- Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures.
(T/F)
a)
T
b)
F
12.
- The hierarchical nature of complex systems is essential to both their design and their description.
(T/F)
a)
T
b)
F
13.
- Both the structure and functioning of a computer are, in essence, simple.
(T/F)
a)
T
b)
F
14.
- A computer must be able to process, store, move, and control data.
(T/F)
a)
T
b)
F
15.
When data are moved over longer distances, to or from a remote device, the process is known as data transport.
(T/F)
a)
T
b)
F
16.
- The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University.
(T/F)
a)
T
b)
F
17.
- John Mauchly and John Eckert designed the ENIAC.
(T/F)
a)
T
b)
F
18.
- The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables.
(T/F)
a)
T
b)
F
19.
- The IAS is the prototype of all subsequent general-purpose computers.
(T/F)
a)
T
b)
F
20.
- The IAS operates by repetitively performing an instruction cycle.
(T/F)
a)
T
b)
F
21.
- Backward compatible means that the programs written for the older machines can be executed on the new machine.
(T/F)
a)
T
b)
F
22.
- A vacuum tube is a solid-state device made from silicon.
(T/F)
a)
T
b)
F
23.
- Computers are classified into generations based on the fundamental hardware technology employed.
(T/F)
a)
T
b)
F
24.
- System software was introduced in the third generation of computers.
(T/F)
a)
T
b)
F
25.
- A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points.
(T/F)
a)
T
b)
F
26.
- IBM's System/360 was the industry's first planned family of computers.
(T/F)
a)
T
b)
F
27.
- Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip.
(T/F)
a)
T
b)
F
28.
- Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components.
(T/F)
a)
T
b)
F
29.
- The Intel x86 evolved from RISC design principles and is used in embedded systems.
(T/F)
a)
T
b)
F
30.
A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS).
(T/F)
a)
T
b)
F
31.
At a top level, a computer consists of CPU, memory, and I/O components.
(T/F)
a)
T
b)
F
32.
- The basic function of a computer is to execute programs.
(T/F)
a)
T
b)
F
33.
- Program execution consists of repeating the process of instruction fetch and instruction execution.
(T/F)
a)
T
b)
F
34.
- Interrupts do not improve processing efficiency.
(T/F)
a)
T
b)
F
35.
- An I/O module cannot exchange data directly with the processor.
(T/F)
a)
T
b)
F
36.
- A key characteristic of a bus is that it is not a shared transmission medium.
(T/F)
a)
T
b)
F
37.
- Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.
(T/F)
a)
T
b)
F
38.
- In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.
(T/F)
a)
T
b)
F
39.
- It is not possible to connect I/O controllers directly onto the system bus.
(T/F)
a)
T
b)
F
40.
- The method of using the same lines for multiple purposes is known as time multiplexing.
(T/F)
a)
T
b)
F
41.
- Timing refers to the way in which events are coordinated on the bus.
(T/F)
a)
T
b)
F
42.
- With asynchronous timing the occurrence of events on the bus is determined by a clock.
(T/F)
a)
T
b)
F
43.
- Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance.
(T/F)
a)
T
b)
F
44.
- The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.
(T/F)
a)
T
b)
F
45.
A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet.
(T/F)
a)
T
b)
F
46.
- No single technology is optimal in satisfying the memory requirements for a computer system.
(T/F)
a)
T
b)
F
47.
- A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external.
(T/F)
a)
T
b)
F
48.
- External memory is often equated with main memory.
(T/F)
a)
T
b)
F
49.
- The processor requires its own local memory.
(T/F)
a)
T
b)
F
50.
- Cache is not a form of internal memory.
(T/F)
a)
T
b)
F
51.
- The unit of transfer must equal a word or an addressable unit.
(T/F)
a)
T
b)
F
52.
- Both sequential access and direct access involve a shared read-write mechanism.
(T/F)
a)
T
b)
F
53.
- In a volatile memory, information decays naturally or is lost when electrical power is switched off.
(T/F)
a)
T
b)
F
54.
- To achieve greatest performance the memory must be able to keep up with the processor.
(T/F)
a)
T
b)
F
55.
- Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words.
(T/F)
a)
T
b)
F
56.
- The L1 cache is slower than the L3 cache.
(T/F)
a)
T
b)
F
57.
- With write back updates are made only in the cache.
(T/F)
a)
T
b)
F
58.
- It has become possible to have a cache on the same chip as the processor.
(T/F)
a)
T
b)
F
59.
- All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions.
(T/F)
a)
T
b)
F
60.
Cache design for HPC is the same as that for other hardware platforms and applications.
(T/F)
a)
T
b)
F
61.
- The basic element of a semiconductor memory is the memory cell.
(T/F)
a)
T
b)
F
62.
- A characteristic of ROM is that it is volatile.
(T/F)
a)
T
b)
F
63.
- RAM must be provided with a constant power supply.
(T/F)
a)
T
b)
F
64.
- The two traditional forms of RAM used in computers are DRAM and SRAM.
(T/F)
a)
T
b)
F
65.
- A static RAM will hold its data as long as power is supplied to it.
(T/F)
a)
T
b)
F
66.
- Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.
(T/F)
a)
T
b)
F
67.
- The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.
(T/F)
a)
T
b)
F
68.
- Semiconductor memory comes in packaged chips.
(T/F)
a)
T
b)
F
69.
- All DRAMs require a refresh operation.
(T/F)
a)
T
b)
F
70.
- A number of chips can be grouped together to form a memory bank.
(T/F)
a)
T
b)
F
71.
- An error-correcting code enhances the reliability of the memory at the cost of added complexity.
(T/F)
a)
T
b)
F
72.
- DRAM is much costlier than SRAM.
(T/F)
a)
T
b)
F
73.
- RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle.
(T/F)
a)
T
b)
F
74.
- The prefetch buffer is a memory cache located on the RAM chip.
(T/F)
a)
T
b)
F
75.
The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data.
(T/F)
a)
T
b)
F
76.
- Magnetic disks are the foundation of external memory on virtually all computer systems.
(T/F)
a)
T
b)
F
77.
- During a read or write operation, the head rotates while the platter beneath it stays stationary.
(T/F)
a)
T
b)
F
78.
- The width of a track is double that of the head.
(T/F)
a)
T
b)
F
79.
- There are typically hundreds of sectors per track and they may be either fixed or variable lengths.
(T/F)
a)
T
b)
F
80.
- A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside.
(T/F)
a)
T
b)
F
81.
- The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector.
(T/F)
a)
T
b)
F
82.
- A removable disk can be removed and replaced with another disk.
(T/F)
a)
T
b)
F
83.
- The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly.
(T/F)
a)
T
b)
F
84.
- The transfer time to or from the disk does not depend on the rotation speed of the disk.
(T/F)
a)
T
b)
F
85.
- RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
(T/F)
a)
T
b)
F
86.
- RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance.
(T/F)
a)
T
b)
F
87.
- Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates.
(T/F)
a)
T
b)
F
88.
- The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
(T/F)
a)
T
b)
F
89.
- SSD performance has a tendency to speed up as the device is used.
(T/F)
a)
T
b)
F
90.
Flash memory becomes unusable after a certain number of writes.
(T/F)
a)
T
b)
F
91.
- A set of I/O modules is a key element of a computer system.
(T/F)
a)
T
b)
F
92.
- An I/O module must recognize one unique address for each peripheral it controls.
(T/F)
a)
T
b)
F
93.
- I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.
(T/F)
a)
T
b)
F
94.
- It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete.
(T/F)
a)
T
b)
F
95.
- With isolated I/O there is a single address space for memory locations and I/O devices.
(T/F)
a)
T
b)
F
96.
- A disadvantage of memory-mapped I/O is that valuable memory address space is used up.
(T/F)
a)
T
b)
F
97.
- The disadvantage of the software poll is that it is time consuming.
(T/F)
a)
T
b)
F
98.
- With a daisy chain the processor just picks the interrupt line with the highest priority.
(T/F)
a)
T
b)
F
99.
- Bus arbitration makes use of vectored interrupts.
(T/F)
a)
T
b)
F
100.
- The rotating interrupt mode allows the processor to inhibit interrupts from certain devices.
(T/F)
a)
T
b)
F
101.
- Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices.
(T/F)
a)
T
b)
F
102.
- When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA).
(T/F)
a)
T
b)
F
103.
- An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.
(T/F)
a)
T
b)
F
104.
- A multipoint external interface provides a dedicated line between the I/O module and the external device.
(T/F)
a)
T
b)
F
105.
A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device.
(T/F)
a)
T
b)
F
106.
- Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture.
(T/F)
a)
T
b)
F
107.
- The end user is concerned mainly with the computer's architecture.
(T/F)
a)
T
b)
F
108.
- The most important system program is the OS.
(T/F)
a)
T
b)
F
109.
- The ABI is the boundary between hardware and software.
(T/F)
a)
T
b)
F
110.
- The OS must determine how much processor time is to be devoted to the execution of a particular user program.
(T/F)
a)
T
b)
F
111.
- With a batch operating system the user does not have direct access to the processor.
(T/F)
a)
T
b)
F
112.
- Privileged instructions are certain instructions that are designated special and can be executed only by the monitor.
(T/F)
a)
T
b)
F
113.
- Uniprogramming is the central theme of modern operating systems.
(T/F)
a)
T
b)
F
114.
- Both batch multiprogramming and time sharing use multiprogramming.
(T/F)
a)
T
b)
F
115.
- An interrupt is a hardware-generated signal to the processor.
(T/F)
a)
T
b)
F
116.
- Swapping is an I/O operation.
(T/F)
a)
T
b)
F
117.
- With demand paging it is necessary to load an entire process into main memory.
(T/F)
a)
T
b)
F
118.
- The Pentium II includes hardware for both segmentation and paging.
(T/F)
a)
T
b)
F
119.
- ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer.
(T/F)
a)
T
b)
F
120.
Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain.
(T/F)
a)
T
b)
F
121.
- Our primary counting system is based on binary digits to represent numbers.
(T/F)
a)
T
b)
F
122.
- The decimal system has a radix of 100.
(T/F)
a)
T
b)
F
123.
- Negative powers of 10 are used to represent the positions of the numbers for decimal fractions.
(T/F)
a)
T
b)
F
124.
- A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.
(T/F)
a)
T
b)
F
125.
- In any number, the rightmost digit is referred to as the most significant digit.
(T/F)
a)
T
b)
F
126.
- A number cannot be converted from binary notation to decimal notation.
(T/F)
a)
T
b)
F
127.
- There are 50 tens in the number 509.
(T/F)
a)
T
b)
F
128.
- The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9.
(T/F)
a)
T
b)
F
129.
- Although convenient for computers, the binary system is exceedingly cumbersome for human beings.
(T/F)
a)
T
b)
F
130.
- A nibble is a grouping of four decimal digits.
(T/F)
a)
T
b)
F
131.
- Hexadecimal notation is only used for representing integers.
(T/F)
a)
T
b)
F
132.
- It is extremely easy to convert between binary and hexadecimal notation.
(T/F)
a)
T
b)
F
133.
- Hexadecimal notation is more compact than binary notation.
(T/F)
a)
T
b)
F
134.
- A sequence of hexadecimal digits can be thought of as representing an integer in base 10.
(T/F)
a)
T
b)
F
135.
Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes.
(T/F)
a)
T
b)
F
136.
- One drawback of sign-magnitude representation is that there are two representations of 0.
a)
T
b)
F
137.
- Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit.
a)
T
b)
F
138.
- It is not necessary for the ALU to signal when overflow occurs.
a)
T
b)
F
139.
- Overflow can only occur if there is a carry.
a)
T
b)
F
140.
- Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software.
a)
T
b)
F
141.
- For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required.
a)
T
b)
F
142.
- Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.
a)
T
b)
F
143.
- Booth's algorithm performs more additions and subtractions than a straightforward algorithm.
a)
T
b)
F
144.
- With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0.
a)
T
b)
F
145.
- An advantage of biased representation is that nonnegative floating-point numbers can be treated as integers for comparison purposes.
a)
T
b)
F
146.
- For base 2 representation, a normal number is one in which the most significant bit of the significand is zero.
a)
T
b)
F
147.
- Actual floating-point representations include a special bit pattern to designate zero.
a)
T
b)
F
148.
- The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers.
a)
T
b)
F
149.
- Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.
a)
T
b)
F
150.
One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.
a)
T
b)
F
151.
- The operation of the digital computer is based on the storage and processing of binary data.
(T/F)
a)
T
b)
F
152.
- Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra.
(T/F)
a)
T
b)
F
153.
- In the absence of parentheses, the AND operation takes precedence over the OR operation.
(T/F)
a)
T
b)
F
154.
- Logical functions are implemented by the interconnection of decoders.
(T/F)
a)
T
b)
F
155.
- The delay by the propagation time of signals through the gate is known as the gate delay.
(T/F)
a)
T
b)
F
156.
- A combinational circuit consists of n binary inputs and m binary outputs.
(T/F)
a)
T
b)
F
157.
- Any Boolean function can be implemented in electronic form as a network of gates.
(T/F)
a)
T
b)
F
158.
- A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form.
(T/F)
a)
T
b)
F
159.
- "Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs.
(T/F)
a)
T
b)
F
160.
- The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU.
(T/F)
a)
T
b)
F
161.
- In general, a decoder has n inputs and 2^n outputs.
(T/F)
a)
T
b)
F
162.
- Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained.
(T/F)
a)
T
b)
F
163.
- Binary addition is exactly the same as Boolean algebra.
(T/F)
a)
T
b)
F
164.
- Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs.
(T/F)
a)
T
b)
F
165.
A register is a digital circuit used within the CPU to store one or more bits of data.
(T/F)
a)
T
b)
F
166.
- One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set.
(T/F)
a)
T
b)
F
167.
- The operation to be performed is specified by a binary code known as the operation code.
(T/F)
a)
T
b)
F
168.
- The address of the next instruction to be fetched must be a real address, not a virtual address.
(T/F)
a)
T
b)
F
169.
- It has become common practice to use a symbolic representation of machine instructions.
(T/F)
a)
T
b)
F
170.
- A high-level language expresses operations in a basic form involving the movement of data to or from registers.
(T/F)
a)
T
b)
F
171.
- One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction.
(T/F)
a)
T
b)
F
172.
- Memory references are faster than register references.
(T/F)
a)
T
b)
F
173.
- The instruction set is the programmer's means of controlling the processor.
(T/F)
a)
T
b)
F
174.
- Addresses are a form of data.
(T/F)
a)
T
b)
F
175.
- Not all machine languages include numeric data types.
(T/F)
a)
T
b)
F
176.
- ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length.
(T/F)
a)
T
b)
F
177.
- Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide.
(T/F)
a)
T
b)
F
178.
- A branch can be either forward or backward.
(T/F)
a)
T
b)
F
179.
- Procedures do not allow programming tasks to be subdivided into smaller units.
(T/F)
a)
T
b)
F
180.
The focus of MMX technology is multimedia programming.
(T/F)
a)
T
b)
F
181.
The value of the mode field determines which addressing mode is to be used.
(T/F)
a)
T
b)
F
182.
- In a system without virtual memory, the effective address is a virtual address or a register.
(T/F)
a)
T
b)
F
183.
- The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field.
(T/F)
a)
T
b)
F
184.
- With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range.
(T/F)
a)
T
b)
F
185.
- Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address.
(T/F)
a)
T
b)
F
186.
- Register indirect addressing uses the same number of memory references as indirect addressing.
(T/F)
a)
T
b)
F
187.
- Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing.
(T/F)
a)
T
b)
F
188.
- The method of calculating the EA is the same for both base-register addressing and indexing.
(T/F)
a)
T
b)
F
189.
- Typically an instruction set will include both preindexing and postindexing.
(T/F)
a)
T
b)
F
190.
- The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages.
(T/F)
a)
T
b)
F
191.
- The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address.
(T/F)
a)
T
b)
F
192.
- The memory transfer rate has not kept up with increases in processor speed.
(T/F)
a)
T
b)
F
193.
- For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.
(T/F)
a)
T
b)
F
194.
- The principal price to pay for variable-length instructions is an increase in the complexity of the processor.
(T/F)
a)
T
b)
F
195.
One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode.
(T/F)
a)
T
b)
F
196.
- The processor needs to store instructions and data temporarily while an instruction is being executed.
(T/F)
a)
T
b)
F
197.
- The control unit (CU) does the actual computation or processing of data.
(T/F)
a)
T
b)
F
198.
- Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.
(T/F)
a)
T
b)
F
199.
- Condition codes facilitate multiway branches.
(T/F)
a)
T
b)
F
200.
- The allocation of control information between registers and memory are not considered to be a key design issue.
(T/F)
a)
T
b)
F
201.
- Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.
(T/F)
a)
T
b)
F
202.
- The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.
(T/F)
a)
T
b)
F
203.
- A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.
(T/F)
a)
T
b)
F
204.
- One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.
(T/F)
a)
T
b)
F
205.
- The predict-never-taken approach is the most popular of all the branch prediction methods.
(T/F)
a)
T
b)
F
206.
- It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.
(T/F)
a)
T
b)
F
207.
- Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.
(T/F)
a)
T
b)
F
208.
- An interrupt is generated from software and it is provoked by the execution of an instruction.
(T/F)
a)
T
b)
F
209.
- While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur.
(T/F)
a)
T
b)
F
210.
The exception modes have full access to system resources and can change modes freely.
(T/F)
a)
T
b)
F
211.
- Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.
(T/F)
a)
T
b)
F
212.
- Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.
(T/F)
a)
T
b)
F
213.
- The major cost in the life cycle of a system is hardware.
(T/F)
a)
T
b)
F
214.
- It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.
(T/F)
a)
T
b)
F
215.
- Procedure calls and returns are not important aspects of HLL programs.
(T/F)
a)
T
b)
F
216.
- The register file is on the same chip as the ALU and control unit.
(T/F)
a)
T
b)
F
217.
- The register file employs much shorter addresses than addresses for cache and memory.
(T/F)
a)
T
b)
F
218.
- To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.
(T/F)
a)
T
b)
F
219.
- Cache memory is a much faster memory than the register file.
(T/F)
a)
T
b)
F
220.
- The cache is capable of handling global as well as local variables.
(T/F)
a)
T
b)
F
221.
- With simple, one cycle instructions, there is little or no need for microcode.
(T/F)
a)
T
b)
F
222.
- When using graph coloring, nodes that share the same color cannot be assigned to the same register.
(T/F)
a)
T
b)
F
223.
- Almost all RISC instructions use simple register addressing.
(T/F)
a)
T
b)
F
224.
- RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.
(T/F)
a)
T
b)
F
225.
Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.
(T/F)
a)
T
b)
F
226.
- The superscalar approach has now become the standard method for implementing high-performance microprocessors.
(T/F)
a)
T
b)
F
227.
- In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.
(T/F)
a)
T
b)
F
228.
- In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.
(T/F)
a)
T
b)
F
229.
- The superscalar approach depends on the ability to execute multiple instructions in parallel.
(T/F)
a)
T
b)
F
230.
- True data dependency is also called flow dependency or read after write (RAW) dependency.
(T/F)
a)
T
b)
F
231.
- Resources include: memories, caches, buses, and register-file ports.
(T/F)
a)
T
b)
F
232.
- Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.
(T/F)
a)
T
b)
F
233.
- The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion).
(T/F)
a)
T
b)
F
234.
- In-order completion requires more complex instruction issue logic than out-of-order completion.
(T/F)
a)
T
b)
F
235.
- The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.
(T/F)
a)
T
b)
F
236.
- Register renaming eliminates antidependencies and output dependencies.
(T/F)
a)
T
b)
F
237.
- In effect, the Pentium 4 architecture implements a CISC instruction set architecture on a RISC microarchitecture.
(T/F)
a)
T
b)
F
238.
- The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.
(T/F)
a)
T
b)
F
239.
- ARM architecture has yet to implement superscalar techniques in the instruction pipeline.
(T/F)
a)
T
b)
F
240.
The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems.
(T/F)
a)
T
b)
F
241.
- Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common, example of parallel organization.
a)
T
b)
F
242.
- The key to the design of a supercomputer or array processor is to recognize that the main task is to perform arithmetic operations on arrays or vectors of floating-point numbers.
a)
T
b)
F
243.
- The term SMP refers to a computer hardware architecture and also to the operating system behavior that reflects that architecture.
a)
T
b)
F
244.
- With multithreading the instruction stream is divided into several smaller streams, known as threads, such that the threads can be executed in parallel.
a)
T
b)
F
245.
- An attractive feature of an SMP is that the existence of multiple processors is transparent to the user.
a)
T
b)
F
246.
- The main drawback of the bus organization is reliability.
a)
T
b)
F
247.
- An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol.
a)
T
b)
F
248.
- With a write-update protocol there can be multiple readers but only one writer at a time.
a)
T
b)
F
249.
- The function of switching applications and data resources over from a failed system to an alternative system in the cluster is referred to as failback.
a)
T
b)
F
250.
- The most important measure of performance for a processor is the rate at which it executes instructions.
a)
T
b)
F
251.
- An SMP operating system manages processor and other computer resources so that the user perceives a single operating system controlling system resources.
a)
T
b)
F
252.
- The objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system.
a)
T
b)
F
253.
- Software cache coherence schemes attempt to avoid the need for additional hardware circuitry and logic by relying on the compiler and operating system to deal with the problem.
a)
T
b)
F
254.
- Both clusters and symmetric multiprocessors provide a configuration with multiple processors to support high-demand applications.
a)
T
b)
F
255.
Snoopy protocols are not suitable for a bus-based multiprocessor.
a)
T
b)
F
256.
- The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.
(T/F)
a)
T
b)
F
257.
- With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.
(T/F)
a)
T
b)
F
258.
- The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.
(T/F)
a)
T
b)
F
259.
- The demand on power requirements has not grown as chip density and clock frequency have risen.
(T/F)
a)
T
b)
F
260.
- As chip transistor density has increased, the percentage of chip area devoted to memory has decreased.
(T/F)
a)
T
b)
F
261.
- The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.
(T/F)
a)
T
b)
F
262.
- Database management systems and database applications are one area in which multicore systems can be used effectively.
(T/F)
a)
T
b)
F
263.
- Even if an individual application does not scale to take advantage of a large number of threads, it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.
(T/F)
a)
T
b)
F
264.
- With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread.
(T/F)
a)
T
b)
F
265.
- The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.
(T/F)
a)
T
b)
F
266.
- An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.
(T/F)
a)
T
b)
F
267.
- A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.
(T/F)
a)
T
b)
F
268.
- The thermal management unit monitors digital sensors for high-accuracy die temperature measurements.
(T/F)
a)
T
b)
F
269.
- The Advanced Programmable Interrupt controller (APIC) monitors thermal conditions and CPU activity and adjusts voltage levels and power consumption appropriately.
(T/F)
a)
T
b)
F
270.
A multicore computer combines two or more processors on a single piece of silicon.
(T/F)
a)
T
b)
F
271.
- A microprogram consists of a sequence of instructions in a microprogramming language.
a)
T
b)
F
272.
- A microprogrammed control unit is a relatively complex logic circuit.
a)
T
b)
F
273.
- Microprogramming became a popular technique for implementing the control unit of CISC processors.
a)
T
b)
F
274.
- To implement a control unit as an interconnection of basic logic elements is a very simple task.
a)
T
b)
F
275.
- A microprogram is midway between hardware and software.
a)
T
b)
F
276.
- It is easier to design in hardware than in firmware.
a)
T
b)
F
277.
- It is more difficult to write a firmware program than a software program.
a)
T
b)
F
278.
- Reading a microinstruction from the control memory is the same as executing that microinstruction.
a)
T
b)
F
279.
- The advantage of horizontal microinstructions is that they are more compact than vertical microinstructions, at the expense of a small additional amount of logic and time delay.
a)
T
b)
F
280.
- The principal advantage of the use of microprogramming to implement a control unit is that it simplifies the design of the control unit.
a)
T
b)
F
281.
- The principal disadvantage of a microprogrammed unit is that it will be somewhat slower than a hardwired unit of comparable technology.
a)
T
b)
F
282.
- It is important to design compact, time-efficient techniques for microinstruction branching.
a)
T
b)
F
283.
- The degree of packing relates to the degree of identification between a given control task and specific microinstruction bits.
a)
T
b)
F
284.
- The PDP-11 is the first member of the LSI-11 family that was offered as a single board processor.
a)
T
b)
F
285.
The TI 8800 Software Development Board is a microprogrammable 32-bit computer card that fits into an IBM PC-compatible host computer.
a)
T
b)
F
286.
- A cycle is made up of a sequence of micro-operations.
a)
T
b)
F
287.
- One technique for implementing a control unit is referred to as hardwired implementation, in which the control unit is a combinatorial circuit.
a)
T
b)
F
288.
- Knowing the machine instruction set does not play a part in knowing the functions that the processor must perform.
a)
T
b)
F
289.
- The control unit controls the operation of the processor.
a)
T
b)
F
290.
- The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program.
a)
T
b)
F
291.
- The execution of a program consists of the sequential execution of instructions.
a)
T
b)
F
292.
- The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other.
a)
T
b)
F
293.
- Each micro-operation of the fetch cycle involves the movement of data into or out of a register.
a)
T
b)
F
294.
- At the completion of the execute cycle a test is made to determine whether any enabled interrupts have occurred, and if they have, the interrupt cycle occurs.
a)
T
b)
F
295.
- The execute cycle is simple and predictable.
a)
T
b)
F
296.
- Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations.
a)
T
b)
F
297.
- For the control unit to perform its function it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system.
a)
T
b)
F
298.
- The control unit is the engine that runs the entire computer.
a)
T
b)
F
299.
the use of common data paths simplifies the interconnection layout and the control of the processor.
a)
T
b)
F
300.
The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.
a)
T
b)
F
100 %
