WorksheetsDDCO QUIZ
Total questions: 20
Worksheet time: 10mins
In a 4-variable K-map, how many cells represent minterms?
8
16
32
64
What is the output of a D Flip-Flop when the input is ‘1’ and a clock pulse is applied?
0
1
High Impedance
No change
Which of the following is not a valid addressing mode?
Immediate
Indexed
Logical
Register
What is the primary purpose of cache memory?
Increase main memory size
Reduce latency
Store backup data
Reduce cost
DMA transfers are controlled by:
CPU
I/O Devices
Memory Controller
DMA Controller
Which operation is performed first in an instruction cycle?
Fetch
Decode
Execute
Write Back
What is the main advantage of using NAND gates for implementation?
Low power consumption
Universality
Speed
High input count
The primary function of a multiplexer is:
Data selection
Data storage
Data amplification
Data inversion
In a 3-to-8 decoder, how many inputs and outputs are present?
2 inputs, 4 outputs
3 inputs, 8 outputs
4 inputs, 16 outputs
3 inputs, 16 output
A flip-flop operates in the:
Asynchronous mode only
Synchronous mode only
Both asynchronous and synchronous modes
Neither asynchronous nor synchronous mode
Which of the following is not a bus arbitration technique?
Daisy chaining
Polling
Interrupt priority
Time-division multiplexing
Bus arbitration ensures:
Equal bandwidth for all devices
Access priority among devices
Permanent ownership of the bus by the CPU
None of the above
The purpose of a program counter (PC) is to:
Store instructions
Hold the address of the next instruction to be executed
Perform calculations
Act as an accumulator
A full-adder can be constructed using:
Two XOR gates and one AND gate
Two half-adders and an OR gate
Three NAND gates
One half-adder and two XOR gates
Which type of flip-flop is used in a Toggling Circuit?
SR Flip-Flop
JK Flip-Flop
D Flip-Flop
Master-Slave Flip-Flop
What is the primary difference between a latch and a flip-flop?
Latches are edge-triggered; flip-flops are level-triggered
Latches are asynchronous; flip-flops are synchronous
Flip-flops require fewer gates than latches
Latches are slower than flip-flops
What is the addressing mode in the instruction ADD A, #5?
Immediate
Direct
Indirect
Indexed
Cache memory is faster than main memory because:
a) It is closer to the CPU
b) It has a smaller size
c) It uses SRAM instead of DRAM
d) All of the above
A 4-to-1 multiplexer requires how many data input lines and select lines?
4 data inputs, 4 select lines
2 data inputs, 2 select lines
2 data inputs, 4 select lines
4 data inputs, 2 select lines
Which of the following is NOT a type of bus used in computer systems?
Data Bus
Address Bus
Cache Bus
Control Bus
