WorksheetsCMSC 133 Written Report Compiled Questions
Total questions: 80
Worksheet time: 3600secs
Name
Class
Date
1.
What is a sign of high CPU usage when the computer is idle?
a)
CPU usage below 10%
b)
CPU usage above 20%
c)
CPU usage above 80% only during heavy tasks
d)
CPU usage fluctuates between 5% and 10%
2.
What is a primary characteristic of superscalar processors?
a)
A) Execute one instruction at a time
b)
B) Utilize multiple instruction pipelines
c)
C) Require only basic scheduling systems
d)
D) Operate without hardware Dependencies
3.
What enables superscalar processors to execute multiple instructions simultaneously?
a)
A) Static scheduling
b)
B) Reduced complexity in design
c)
C) Single instruction pipelines
d)
D) Instruction-level parallelism (ILP)
4.
Which feature allows superscalar processors to handle more tasks?
a)
A) Single instruction pipelines
b)
B) Simplified control flow
c)
C) Multiple instruction pipelines
d)
D) Limited hardware scheduling
5.
What is the role of smart scheduling systems in superscalar processors?
a)
A) To simplify instruction dependencies
b)
B) To analyze and resolve instruction dependencies for efficient execution
c)
C) To increase hardware complexity without improving performance
d)
D) To reduce parallelism in instruction Execution
6.
What is the purpose of register renaming in superscalar processors?
a)
A) To eliminate control hazards
b)
B) To resolve false dependencies like Write-After-Write (WAW)
c)
C) To simplify the hardware design
d)
D) To reduce the need for branch Prediction
7.
How does superscalar processing differ from super-pipelining?
a)
A) Handles parallel instructions
b)
B) Issues multiple instructions per cycle
c)
C) Only uses static scheduling
d)
D) Focuses on dependencies
8.
What is Out-of-Order Execution?
a)
A) Executing in program order
b)
B) Executing independently of program order
c)
C) Avoiding parallelism
d)
D) Disabling resources
9.
Which dependency is associated with Read-After-Write (RAW) hazards?
a)
A) True data dependency
b)
B) Anti-dependency
c)
C) Output dependency
d)
D) Resource conflict
10.
What is an example of a resource conflict in superscalar processors?
a)
A) A procedural branch misprediction
b)
B) Two instructions requiring the same Arithmetic Logic Unit (ALU)
c)
C) An instruction waiting for a register to be read
d)
D) False dependencies due to multiple pipeline registers
11.
Which branch prediction technique uses historical behavior for accuracy?
a)
A) Static branch prediction
b)
B) Delayed branching
c)
C) Dynamic branch prediction
d)
D) Sequential execution
12.
What hazard occurs when two instructions compete for the same resource simultaneously?
a)
Data Hazard
b)
Structural Hazard
c)
Control Hazard
d)
Name Dependency
13.
Which of the following is an example of a control hazard solution?
a)
Register renaming
b)
Delayed branching
c)
Pipeline forwarding
d)
Output dependency
14.
What is a common cause of overheating in a computer?
a)
Outdated software
b)
High CPU usage
c)
Blocked air vents
d)
All of the above
15.
What is a mitigation strategy for input overvoltage?
a)
A. Use external filtering circuits
b)
B. Employ Undervoltage protection (UVP)
c)
C. Install surge suppressors
d)
D. Both b and c
16.
What is a potential sign of high CPU usage when performing tasks that are not resource-heavy?
a)
CPU operates silently
b)
CPU usage drops below 10%
c)
Sluggish computer performance
d)
Mouse responsiveness improves
17.
What type of pipelining hazard occurs when one instruction depends on the result of a previous instruction still in the pipeline?
a)
Structural Hazard
b)
Data Hazard
c)
Control Hazard
d)
Branch Prediction
18.
What is a key risk associated with overclocking a CPU?
a)
Improved system cooling
b)
Increased CPU lifespan
c)
Reduced CPU lifespan
d)
More efficient multitasking
19.
Which of the following symptoms might indicate a failing CPU?
a)
A blue screen with an error code
b)
Increased storage capacity
c)
Improved battery performance
d)
Faster startup times
20.
What is a mitigation strategy for preventing reversed polarity issues in a power supply unit (PSU)?
a)
Utilize Undervoltage protection (UVP)
b)
Use diodes to block reverse currents
c)
Ensure external components are missing
d)
Increase heat generation
21.
What is the primary goal of Instruction-Level Parallelism (ILP)?
a)
To reduce memory usage
b)
To enable simultaneous execution of instructions
c)
To minimize the number of processor cores
d)
To improve software reliability
22.
Which hardware structure is responsible for keeping track of instruction completion in out-of-order execution?
a)
Branch Predictor
b)
Reorder Buffer (ROB)
c)
Floating Point Unit
d)
Instruction Decoder
23.
What is the main drawback of speculative execution in ILP?
a)
Increased latency in executing instructions
b)
Lower branch prediction accuracy
c)
Wasted energy on incorrect predictions
d)
Reduced memory bandwidth
24.
According to Amdahl’s Law, why are performance gains from ILP limited?
a)
Instructions cannot always be reordered.
b)
Serial portions of programs dominate execution time.
c)
Memory bandwidth does not scale with cores.
d)
Pipelines increase misprediction penalties.
25.
What type of branch predictor adapts to program behavior by tracking past branch outcomes?
a)
Static Predictor
b)
Tournament Predictor
c)
Dynamic Predictor
d)
Bimodal Predictor
26.
Which of the following is NOT a challenge associated with scaling ILP in multi-core processors?
a)
Memory contention between cores
b)
Increased complexity of NUMA architectures
c)
Limited serial portions of programs
d)
Leakage currents in smaller process nodes
27.
What technique minimizes the need to repeatedly fetch frequently used operations in AMD Zen microarchitecture?
a)
Dynamic Branch Prediction
b)
Micro-op Cache
c)
Reorder Buffer
d)
Superscalar Execution
28.
How do pipeline flushes impact processors during branch mispredictions?
a)
They reduce energy efficiency by discarding incorrectly executed instructions.
b)
They delay branch prediction by rerunning all instructions.
c)
They allow parallel execution of new instructions.
d)
They double the latency of completed instructions.
29.
What is one way future processors aim to improve branch prediction accuracy?
a)
Use of machine learning techniques
b)
Static prediction of branch outcomes
c)
Reducing the size of instruction windows
d)
Limiting speculative execution
30.
Which field heavily relies on ILP to process massive matrix multiplications efficiently?
a)
High-Performance Computing
b)
Machine Learning and AI
c)
Gaming
d)
Processor Cooling Technology
31.
What is a micro-operation?
a)
A large task performed by the ALU
b)
The smallest functional task performed by the CPU's control unit
c)
A method to store data in memory
d)
An input/output device operation
32.
What is the first phase of the instruction cycle?
a)
Decode
b)
Execute
c)
Fetch
d)
Write-back
33.
What is the role of control signals?
a)
To guide the CPU on what to do
b)
To charge the computer battery
c)
To display images on the screen
d)
To send emails
34.
What does the Fetch stage do?
a)
Performs the addition of two numbers
b)
Moves the instruction from memory to the CPU
c)
Displays a message on the screen
d)
Stores data in memory
35.
What is the function of the Memory Read (MR) signal?
a)
To save data into memory
b)
To retrieve data from memory
c)
To turn off the computer
d)
To clear a register
36.
What does a hardwired control unit use to generate control signals?
a)
A set of instructions stored in memory
b)
Fixed hardware circuits
c)
Data from the internet
d)
The user’s input
37.
Which component performs arithmetic and logic operations in a CPU?
a)
ALU (Arithmetic Logic Unit)
b)
Memory
c)
Control Bus
d)
I/O Device
38.
What type of control signal is used to shift the value in a register to the left?
a)
Memory Write
b)
Shift
c)
Rotate
d)
Increment
39.
Which of the following is an example of a micro-operation?
a)
Moving data from one register to another
b)
Installing an operating system
c)
Writing an email
d)
Connecting to Wi-Fi
40.
Micro-operations are typically executed during which CPU process?
a)
Writing data to a file
b)
Instruction cycle stages like Fetch, Decode, or Execute
c)
Running an external program
d)
Connecting to a network
41.
Which of the following advantages of pipelining defines its efficient use of resources that can reduce overall operational costs?
a)
Cost Effectiveness
b)
Scalability
c)
Faster Execution
d)
Support for Advanced Computing Needs
42.
How does pipelining execute multiple instructions simultaneously?
a)
having its own set of resources to perform operations in parallelism and improve the performance of the processors
b)
compressing them into one task to execute at the same time
c)
distributing tasks across multiple processors
d)
breaking down each instruction into separate, overlapping stages that allow the processor to work on different instructions at a time
43.
Each ____ processes a new instruction as it progresses through the pipeline stages.
a)
step
b)
processor
c)
minute
d)
clock cycle
44.
At which stage of pipelining are the operands read and written to present in the instruction?
a)
Instruction Execute
b)
Memory Fetch
c)
Instruction Fetch
d)
Instruction Decode
45.
Pipelining is a standard feature in ____ processors, which utilizes the 5-stage instruction whereas _____ processors do not support parallelism and pipelining.
a)
RISC; CISC
b)
CISC; RISC
c)
RISC; LC3
d)
LC3; RISC
46.
Which one of the following is NOT a data hazard?
a)
Read after Read (RAR)
b)
Write after Read (WAR)
c)
Write after Write (WAW)
d)
Read after Write (RAW)
47.
______ occur when multiple instructions compete for the same hardware resource simultaneously, such as memory or functional units.
a)
Control Hazard
b)
Hardware Hazard
c)
Structural Hazard
d)
Data Hazard
48.
At which stage of pipelining does the processor get instructions from memory and loads it into a special register?
a)
Memory Access
b)
Instruction Decode
c)
Instruction Fetch
d)
Write Back
49.
The following tasks benefit pipelining’s support for advanced computing needs (high-speed computations due to its optimized nature) EXCEPT for one.
a)
Graphics processing
b)
Artificial intelligence
c)
Big data analysis
d)
Optimizing hardware resources
50.
This feature allows for minimization of idle time and improvement of execution time.
a)
Increased Throughput
b)
Faster Execution
c)
Scalability
d)
Support for Advanced Computing Needs
51.
What is included in the thread context?
a)
Open files, global variables, and thread priority
b)
CPU registers, stack, and program counter
c)
CPU registers, global data, and program counter
d)
Heap memory, thread ID, and process code
52.
How does Thread-Level Parallelism (TLP) differ from Instruction-Level Parallelism (ILP)?
a)
TLP focuses on reordering instructions within a single thread, while ILP uses multiple cores.
b)
TLP relies on pipelining, whereas ILP requires shared memory multiprocessors.
c)
TLP explicitly uses multiple threads of execution, while ILP exploits parallelism within a single thread.
d)
TLP is implicit and handled by the compiler, while ILP is explicitly defined by the programmer.
53.
What is a thread in the context of CPU utilization?
a)
The smallest unit of CPU execution
b)
A hardware feature used to execute multiple processes simultaneously
c)
A process that runs independently with its own memory space and files
d)
A lightweight task that shares no resources with other threads in the process.
54.
Which of the following best describes the role of Thread-Level Parallelism (TLP) in server environments and web applications?
a)
It limits server capabilities to reduce system overhead.
b)
It allows servers to process only one task at a time.
c)
It enhances responsiveness and scalability by distributing tasks across multiple threads.
d)
It eliminates the need for database management in web applications.
55.
What role do advances in compiler technologies play in TLP?
a)
Simplifying single-thread execution
b)
Automating the parallelization of code
c)
Reducing the need for multi-core processors
d)
Increasing the need for manual parallelization
56.
Which category in Flynn’s Taxonomy is best suited for vector and matrix operations?
a)
SISD
b)
SIMD
c)
MISD
d)
MIMD
57.
What is a key feature of MISD systems?
a)
Executing multiple instructions on multiple datasets
b)
Executing the same instruction on multiple datasets
c)
Executing multiple instructions on a single dataset
d)
Sequential execution of instructions
58.
How does MIMD architecture handle memory?
a)
Only shared memory
b)
Only distributed memory
c)
Both shared and distributed memory
d)
No memory is shared
59.
Which of the following is a challenge in managing thread-level parallelism (TLP) related to hardware design?
a)
Memory Contention
b)
Cache Coherence
c)
Task Granularity
d)
Real-Time Constraints
60.
Which of the following best describes a performance limitation in thread-level parallelism (TLP) according to Amdahl's Law?
a)
Increased synchronization overhead with higher thread counts
b)
Diminishing returns in performance as the number of threads increases
c)
Increased resource contention between threads
d)
Load imbalance causes some threads to idle while others work
61.
What is a chip multiprocessing?
a)
Switching threads in one core
b)
Using multiple cores on a chip
c)
Running one thread at a time
d)
Combining all threads into one process
62.
What is a process?
a)
A simple task performed by the CPU
b)
A thread running inside the processor
c)
A program running with its own memory and resources
d)
A hardware feature for faster execution
63.
What is the primary advantage of simultaneous multithreading (SMT)?
a)
It reduces hardware complexity
b)
It utilizes all available execution slots for maximum efficiency
c)
It simplifies the compiler’s task
d)
It eliminates thread-switch delays entirely
64.
What is the key feature of threads?
a)
Threads do not share resources
b)
Threads run in separate processors only
c)
Threads require no operating system support
d)
Threads share memory and resources
65.
What is VLIW used for?
a)
Running multiple instructions in one word
b)
Switching threads faster
c)
Slowing down instructions for accuracy
d)
Combining all threads in one process
66.
Why is a thread switch faster than a process switch?
a)
Threads share resources, so less data is moved
b)
Threads run in separate cores
c)
Processes take less memory than threads
d)
Threads require fewer instructions
67.
What is the main feature of blocked thread multithreading?
a)
Running all threads together
b)
Using a single thread for all tasks
c)
Switching threads when one is stalled
d)
Switching between threads every cycle
68.
Which of the following describes a user-level thread?
a)
Managed by the operating system
b)
Managed by applications
c)
Runs on separate processor
d)
Require kernel-level support
69.
What is a thread?
a)
A physical core in the processor
b)
A hardware feature for fast computing
c)
A lightweight unit of work within a process
d)
A program that owns resources and memory
70.
What is the primary measure of processor performance?
a)
Clock Frequency
b)
Number of Threads
c)
Instruction Complexity
d)
Millions Instructions Per Second (MIPS)
71.
Which of the following best defines data parallelism?
a)
Performing different operations on the same dataset simultaneously.
b)
Applying the same operation to multiple pieces of data simultaneously.
c)
Executing multiple instruction streams on a single data stream.
d)
Dividing a single task among multiple processors for independent execution.
72.
Which modern system is most commonly associated with leveraging data parallelism?
a)
Central Processing Units (CPUs)
b)
Graphics Processing Units (GPUs)
c)
Distributed Databases
d)
Cache Memory Systems
73.
Which of the following parallelism classes does Hybrid Parallelism explicitly incorporate?
I. Data Parallelism
III. Instruction Level Parallelism
II. Bit-Level Parallelism
IV. Task Parallelism
a)
I and III
b)
III and II
c)
IV and I
d)
II and IV
74.
Which of the following is an example of an architecture that utilizes hybrid parallelism?
a)
CPU+GPU Systems
b)
Accelerators in HPCs
c)
Shared Memory Systems with Multicore CPUs
d)
Real-time 3D Rendering
75.
What is the primary goal of increasing bit-level parallelism in processors?
a)
To reduce the number of instructions required for larger data operations
b)
To simplify software development
c)
To enhance instruction-level parallelism
d)
To decrease memory size requirements
76.
Which of the following advancements marked the first bit-parallel system?
a)
Introduction of 4-bit processors in the 1970s
b)
Development of VLSI technology
c)
Release of the 16-bit Whirlwind computer in 1951
d)
Launch of 64-bit systems like the Nintendo 64
77.
Determine which is a key benefit of Instruction Level Parallelism (ILP).
a)
Increases throughput by running multiple instructions in each clock cycle
b)
Increases Hardware complexity
c)
Promotes Scalability
d)
Decreases hardware utilization
78.
It is a technique of Instruction Level Parallelism that divides execution of instructions into several phases.
a)
Out-of-order execution
b)
Pipelining
c)
Superscalar
d)
Dynamic Instruction Scheduling
79.
What is task parallelism?
a)
Applying the same operation to different data subsets
b)
Executing distinct tasks concurrently on multiple processors
c)
Eliminating communication between tasks
d)
Running sequential operations on one processor
80.
Which is an example of task parallelism?
a)
Filtering a dataset in parallel
b)
Concurrently handling AI, physics, and rendering in a game
c)
Summing elements of an array across cores
d)
Encoding video frames simultaneously
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