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WorksheetsEmbedded Systems I/O Programming Quiz
Total questions: 16
Worksheet time: 12mins
Are all devices on an embedded computer other than the CPU classified as I/O devices? Why or why not?
Yes, all devices except the CPU are I/O devices.
No, devices like memory, DMA controllers, and timers are not considered I/O devices.
Yes, I/O devices include memory and internal devices like DMA controllers.
No, only devices directly connected to the CPU are I/O devices.
Why are some registers only readable while others are both readable and writable?
Writable registers are more efficient than read-only registers.
Writable registers are used for debugging only.
Read-only registers prevent accidental modification of critical information.
Writable registers serve no practical purpose.
What is the key difference between busy-wait I/O and interrupt-driven I/O?
Interrupt-driven I/O requires polling, while busy-wait does not.
Busy-wait I/O blocks the CPU, while interrupt-driven I/O allows the CPU to perform other tasks.
Interrupt-driven I/O is slower than busy-wait I/O.
Busy-wait I/O is more power-efficient than interrupt-driven I/O.
What is a parity check, and why is it important in communication systems?
A method to compress data for faster transmission.
A technique to encrypt data for security.
A simple error-detection method to ensure data integrity.
A way to prioritize communication channels.
How does memory-mapped I/O enable communication between the CPU and peripherals?
By using dedicated instructions for I/O operations.
By mapping device registers into the CPU’s main memory space for standard load/store instructions.
By polling the peripherals continuously.
By using interrupts for every data transaction.
Why is debugging interrupt handlers more challenging than debugging regular routines?
Interrupt handlers run slower than regular routines.
Interrupts execute synchronously, making timing issues easy to identify.
The asynchronous and unpredictable timing of interrupts complicates debugging.
Interrupt handlers require dedicated debugging hardware.
What triggers the DMA controller for data transfer?
A software signal from the CPU.
A clock pulse from the system timer.
An I/O device request or a CPU configuration signal.
A signal from the memory bus.
How does the CPU determine which interrupt to service first when multiple interrupts occur simultaneously?
By servicing the first interrupt received.
Based on priority levels assigned to interrupts using NVIC or similar controllers.
By polling each interrupt line for service requests.
By ignoring low-priority interrupts.
Can interrupts interrupt each other? How are nested interrupts handled?
No, interrupts cannot preempt each other.
Yes, higher-priority interrupts can preempt lower-priority ISRs, and context is saved on the stack.
No, once an interrupt is in progress, all others are masked.
Yes, but only if the NVIC allows preemption.
What role does NVIC play in handling multiple interrupts?
It disables all interrupts for low-priority tasks.
It assigns static priority levels to each interrupt.
It manages interrupt priorities and enables nested interrupts.
It prevents interrupts from preempting ongoing tasks.
What is DMA, and how does it change CPU involvement in data transfers?
DMA eliminates the need for a CPU entirely.
DMA handles data transfers between memory and devices, freeing the CPU for other tasks.
DMA requires the CPU to initiate every transfer.
DMA slows down data transfers compared to CPU-driven methods.
How does the SysTick Timer’s auto-reload functionality support real-time applications?
It allows developers to manually reload the timer for periodic tasks.
It generates periodic interrupts automatically without software intervention.
It only works with external clock sources.
It delays periodic tasks to reduce system load.
Why is the SysTick Timer often used with RTOS for task scheduling?
It enables precise, periodic interrupts for task scheduling.
It simplifies task prioritization.
It improves clock speed for the CPU.
It eliminates the need for hardware timers.
How does the integration of NVIC and SysTick Timer enhance embedded systems?
By increasing the CPU’s clock speed.
By providing precise periodic interrupts and enabling efficient task prioritization and switching.
By reducing memory requirements.
By eliminating the need for external timers.
How does the use of interrupts improve system performance in embedded systems?
By enabling the CPU to respond to events without polling.
By increasing the clock speed of the CPU.
By allowing the CPU to execute tasks sequentially.
By reducing the number of I/O devices needed.
What is the significance of using a watchdog timer in embedded systems?
To enhance the speed of data transfers.
To monitor the CPU's temperature.
To manage power consumption effectively.
To reset the system in case of software malfunctions.
