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WorksheetsVerilog Fundamentals Assessment
Total questions: 10
Worksheet time: 5mins
What is the basic syntax for defining a module in Verilog?
define module_name (input port_list, output port_list) { // module body }
module_name (output port_list, input port_list); begin // module body endmodule
module module_name (input port_list, output port_list); begin // module body endmodule
module module_name; input port_list; output port_list; endmodule
How do you declare a wire and a reg in Verilog?
wire myWire reg myReg;
wire myWire; reg myReg;
wire myReg; reg myWire;
reg myWire; wire myReg;
What is the difference between combinational and sequential logic?
Sequential logic has no memory and depends only on current inputs; combinational logic has memory.
Combinational logic is slower than sequential logic due to its complexity.
Combinational logic uses past states; sequential logic uses only current inputs.
Combinational logic has no memory and depends only on current inputs; sequential logic has memory and depends on current inputs and past states.
Describe how a multiplexer can be implemented in Verilog.
module mux2to1(input wire a, input wire b, input wire sel); output wire y; assign y = (b) ? a : sel; endmodule
module mux2to1(input wire a, input wire b, input wire sel, output wire y); assign y = (sel) ? b : a; endmodule
module mux2to1(input wire a, input wire b, input wire sel, output wire y); y = a & b; endmodule
module mux4to1(input wire a, input wire b, input wire sel, output wire y); assign y = (a) ? b : sel; endmodule
What is a flip-flop and how is it represented in Verilog?
A flip-flop is a digital memory circuit represented in Verilog using an 'always' block triggered by a clock signal.
A flip-flop is an analog circuit represented in Verilog using a 'module' declaration.
A flip-flop is a type of resistor used in digital circuits.
A flip-flop is a memory device that operates without a clock signal.
Explain the concept of a finite state machine (FSM).
A finite state machine (FSM) is a type of algorithm that only processes numerical data.
A finite state machine (FSM) is a computational model with a finite number of states and transitions based on input.
A finite state machine (FSM) is a graphical representation of a computer's hardware components.
A finite state machine (FSM) is a model that can have an infinite number of states.
How do you define states and transitions in a Verilog FSM?
States are defined in a separate module; transitions are managed through function calls.
States are defined as boolean values; transitions are handled with for loops.
States are defined using integers; transitions are implemented with if statements.
States are defined as unique identifiers; transitions are implemented using case statements in an always block.
What is the purpose of a testbench in Verilog?
To optimize the design for better performance.
The purpose of a testbench in Verilog is to simulate and verify the functionality of a design.
To create a graphical user interface for the design.
To generate random input data for the design.
How do you simulate a Verilog design using a testbench?
Instantiate the design in a testbench, apply stimulus, and run the simulation.
Use a simulation tool without any code
Only apply stimulus without instantiation
Run the design without a testbench
What are some common simulation techniques used in Verilog?
Testbenches, behavioral modeling, structural modeling.
Code optimization methods
Debugging techniques
Synthesis tools
