WorksheetsFlip Flop
Total questions: 10
Worksheet time: 5mins
The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Sequential circuit contains
a) No memory element
b) Atleast one memory element
c) All inputs applied simultaneously
d) None of the above
T Flip flop is used as
Transfer data circuit
Toggle switch
Time delay switch
None of the above
A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
The advantage of a J-K flip-flop over an S-R FF is that ________.
A.it has fewer gates
B.it has only one output
C.it has no invalid states
D.it does not require a clock input
Following flip flop is used to eliminate race around problem
SR Flip flop
JK Flip flop
Master Slave Flip flop
D Flip flop
