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WorksheetsVerilog Quizz
Total questions: 20
Worksheet time: 3mins
Verilog is an
Case Insensitive
Case Sensitive
Can't say
Integer datatype is allocated ______ number of bits
16
32
64
8
reg [4:1] pwm will initialize variable of _______ bits
3
4
5
6
{,} is used to perform which operation
concat
Division
Exponent
Mod
The most appropriate modeling style to implement Traffic light controller will be
Dataflow
Structural
Behavioral
Switch
Full of HDL is.......and two HDL Languages are ........and ..................
Hardware developed language
VHLD
Verilog
Hardware debugging language
Verilag HDL
VHDL
Hardware description
Language
Verilog
C
Hardware description
Language
Verilog
VHDL
Describe the structure of a testbench in Verilog.
A testbench in Verilog does not need to instantiate the DUT.
A testbench in Verilog consists only of a module declaration and no signal declarations.
A testbench in Verilog includes a module declaration, signal declarations, instantiation of the DUT, initial and always blocks for stimulus and monitoring, and simulation control.
A testbench requires only a single always block for stimulus and monitoring.
Special identifiers reserved to define the language constructs are called?
Registers
system tasks.
keywords
whitespaces
For describing circuits like flip flops _____________ statement is used
always
assign
initial
forever
<= is used in
Blocking
Non Blocking
Both
None
Which logic level is not supported by
verilog?
U
X
Z
None of the above
Which level of abstraction level is available in Verilog but not in VHDL?
Behavioral level
Structural level
Dataflow level
Switch level
The input and output ports should be declared inside the ________
Module
Case
wire
None of the above
The symbol used for Logical AND operation is ______
and
or
&&
None
In behavioral modeling the keyword used is _______
always
become
and
or
The Verilog HDL code ends with the keyword_________
always
module
keys
endmodule
What are the different types of operators available in Verilog?
Arithmetic, bitwise, logical, and relational operators
Comparison, assignment, increment, decrement operators
Addition, subtraction, multiplication, division operators
String, array, object, function operators
always will be used in program when we use following data type
wire
value set
register
integer
Half adder will be using following gates to the circuit
XOR & AND gate
XOR & OR gate
NOT & XOR gate
NAND & XOR gate
Which of the following data types can store value during Verilog simulation?
wire
wand
wor
reg
