Worksheets20EC214 - QUIZ-2
Total questions: 10
Worksheet time: 3mins
The temporal variation of the clock period at a given point that is clock period is expand or reduce on a cycle by cycle is refered as ___________
Clock Skew
Clock rate
Clock jitter
None of the above
The clock skew can be positive or negative depending upon the ___________ and
____________ of the clock source.
level of spatial variation and position
routing direction and position
phase of the spatial variation and direction
phase of the spatial variation and position
Which is not a sources of clock skew and jitter?
Clock Signal Generation
Manufacturing Device Variations
Interconnect Variations
Device Scaling
In most high-speed digital processors, a major-
ity of the power is dissipated in the _______________.
Switching
Clock Network
Device Ideal Condition
All the Above
Latch Based designs are preferred in case of clock frequency in ______
KHz
MHz
GHz
THz
The logical ordering of the operations is ensured by the acknowledge-request scheme __________
handshaking protocol
Simple Mail Transfer Protocol
Challenge-Handshake Authentication Protocol
Dial-up Internet Access
The four events proceed in a cyclic order in the process of self timed signalling are ________
data change
request
data acceptance
All the above
An asynchronous signal must be resolved to be either in the high or low state before it is fed into the synchronous environment. A circuit that implements such a decision making function is called a ___________
Arbiters
Synchronizers
Loop Filter
XOR Phase Detectors
Which is not an building block of PLL?
VCO
Phase Detector
Arbiters
Phase Frequency Detector
The connection of synchronous and asynchronous components introduces the risk of ____
synchronization failure
Acceptable Failure
Mean time to failure
instantaneous failure
