WorksheetsCHAPTER 7 MODEL OF DIGITAL IC DESIGN
Total questions: 40
Worksheet time: 3mins
Name
Class
Date
1.
An NMOS transistor turns on when
a)
The gate is at logic 0 (GND)
b)
The gate is at logic 1 (V_DD)
c)
The drain is at logic 0 (GND)
d)
The drain is at logic 1 (V_DD)
2.
A PMOS transistor turns on when
a)
The gate is at logic 1 (V_DD)
b)
The gate is at logic 0 (GND)
c)
The drain is at logic 0 (GND)
d)
The drain is at logic 1 (V_DD)
3.
Miller capacitance is
a)
Capacitance between gate and source
b)
Capacitance between gate and drain
c)
Capacitance between gate and body
d)
Capacitance between source and drain
4.
How does Miller capacitance affect MOSFET operation?
a)
Increases switching speed
b)
Decreases switching speed
c)
Does not affect switching speed
d)
Stabilizes output voltage
5.
The effective capacitance of a MOSFET during switching is
a)
Equal to gate-to-drain capacitance
b)
Equal to gate-to-source capacitance
c)
Twice the gate-to-drain capacitance
d)
Twice the gate-to-source capacitance
6.
The effective switching resistance of a long-channel MOSFET is determined by
a)
Resistance between gate and drain
b)
Resistance between gate and source
c)
Resistance between source and drain
d)
Resistance between gate and substrate
7.
The effective switching resistance of a short-channel MOSFET depends on
a)
Channel length
b)
Channel width
c)
On-state current (I_on)
d)
Both channel length and width
8.
When V_GS > V_DD/2, the MOSFET will
a)
Turn on
b)
Turn off
c)
Operate unstably
d)
Remain unchanged
9.
The characteristic switching time constant (Ï„_n) is determined by
a)
R_n and C_ox
b)
V_GS and V_DD
c)
Resistance and capacitance between gate and source
d)
Channel length and width
10.
The effective switching resistance of a PMOS is greater than that of an NMOS due to
a)
Higher intrinsic resistance
b)
Higher hole mobility
c)
Higher electron mobility
d)
Smaller size
11.
Capacitance effects impact
a)
Switching speed
b)
Input voltage
c)
Output voltage
d)
Current through the MOSFET
12.
The capacitance between the gate and drain of a MOSFET is
a)
Overlap capacitance from lateral diffusion
b)
Overlap capacitance from residual diffusion
c)
Depletion region capacitance
d)
Accumulation region capacitance
13.
The effective switching resistance of a long-channel MOSFET is determined by the equation
a)
R = V/I
b)
R = 1/(λI_D)
c)
R = (V_DD − V_TH)/I_D
d)
R = 1/(K_p · (W/L) · (V_GS − V_TH))
14.
The gate-to-drain capacitance in the triode region of a MOSFET is
a)
C_ox
b)
C_ox/2
c)
2C_ox
d)
Undefined
15.
When the channel length of a short-channel MOSFET increases, the switching resistance
a)
Increases
b)
Decreases
c)
Remains unchanged
d)
Changes unpredictably
16.
The capacitance C_ox is determined by
a)
Channel length and width
b)
Oxide layer thickness
c)
Voltage between gate and source
d)
All of the above
17.
The characteristic switching time constant (Ï„_n) increases when
a)
Channel length decreases
b)
Channel length increases
c)
Supply voltage decreases
d)
Supply voltage increases
18.
The effective switching resistance of a short-channel MOSFET depends on
a)
Channel length
b)
Channel width
c)
On-state current (I_on)
d)
Both channel length and width
19.
The gate-to-source capacitance of a MOSFET in the triode region is
a)
C_ox
b)
C_ox/2
c)
2C_ox
d)
Undefined
20.
The effective switching resistance of a long-channel MOSFET depends on
a)
Channel length
b)
Channel width
c)
Current through the MOSFET
d)
Voltage between gate and source
21.
The Miller effect in a MOSFET primarily affects
a)
Switching speed
b)
Input voltage
c)
Output voltage
d)
Current through the MOSFET
22.
The output resistance of a MOSFET in the saturation region depends on
a)
Gate resistance
b)
Source resistance
c)
Drain resistance
d)
Current through the MOSFET
23.
The gate-to-source capacitance of a MOSFET in the saturation region is
a)
C_ox
b)
C_ox/2
c)
Undefined
d)
2C_ox
24.
The effective switching resistance of a PMOS compared to an NMOS is
a)
Smaller
b)
Larger
c)
Equal
d)
Cannot be determined
25.
When V_GS < V_DD/2, the MOSFET will
a)
Turn on
b)
Turn off
c)
Operate unstably
d)
Remain unchanged
26.
The effective switching resistance of a PMOS compared to an NMOS is
a)
Smaller
b)
Larger
c)
Equal
d)
Cannot be determined
27.
The threshold voltage of a CMOS inverter gate is
a)
The voltage at which the MOSFET transitions from off to on
b)
The voltage at which the drain current reaches its maximum
c)
The voltage at which the inverter switches from logic high to logic low
d)
The voltage at which the inverter begins consuming power
28.
When the input of a CMOS inverter is GND, the output will be
a)
GND
b)
V_DD
c)
A value between GND and V_DD
d)
Undefined
29.
The switching point (V_SP) of a CMOS inverter is determined when
a)
Input voltage equals output voltage
b)
Input voltage is less than the threshold voltage
c)
Output voltage is greater than the threshold voltage
d)
Current through the MOSFET reaches its maximum
30.
The high-level logic noise margin (NM_H) of a CMOS inverter is
a)
The difference between V_OH and V_IH
b)
The difference between V_OL and V_IL
c)
The difference between V_DD and V_OH
d)
The difference between GND and V_OL
31.
Latch-up in a CMOS inverter can be mitigated by
a)
Reducing the threshold voltage
b)
Reducing parasitic resistance and optimizing the layout of connections between PMOS and NMOS
c)
Increasing parasitic resistance
d)
Increasing input voltage
32.
Parasitic capacitance in a CMOS inverter primarily affects
a)
Propagation delay
b)
Input voltage
c)
Output voltage
d)
Current through the MOSFET
33.
The V_OH voltage of a CMOS inverter is
a)
Input voltage
b)
Highest output voltage
c)
Lowest output voltage
d)
Threshold voltage
34.
The V_OL voltage of a CMOS inverter is
a)
Input voltage
b)
Highest output voltage
c)
Lowest output voltage
d)
Threshold voltage
35.
The effective switching resistance of a CMOS inverter is
a)
Resistance of the NMOS gate
b)
Resistance of the PMOS gate
c)
Combined resistance of both NMOS and PMOS during switching
d)
Resistance of the substrate
36.
The Miller effect in a CMOS inverter affects
a)
Input voltage
b)
Output voltage
c)
Effective capacitance
d)
Current through the MOSFET
37.
The effective input capacitance of a CMOS inverter is determined by
a)
NMOS gate
b)
PMOS gate
c)
Total capacitance of both NMOS and PMOS gates
d)
Capacitance between gate and source
38.
During switching, a CMOS inverter may be affected by
a)
Temperature
b)
Parasitic capacitance
c)
Supply voltage
d)
All of the above
39.
The output resistance of a CMOS inverter in the saturation region depends on
a)
NMOS resistance
b)
PMOS resistance
c)
Combined resistance of both NMOS and PMOS
d)
Substrate resistance
40.
A buffer circuit in a CMOS inverter is used to
a)
Reduce propagation delay
b)
Increase resistance
c)
Reduce input voltage
d)
Increase output current
100 %
