WorksheetsDigital electronics
Total questions: 68
Worksheet time: 1hrs 3mins
The time required for a pulse to go from LOW level to HIGH level is called
rise time
fall time
bit time
pulse width
the time required for the transition from the HIGH level to LOW level is called
rise time
fall time
bit time
pulse width
the measure of duration of the pulse and is often defined as the time interval between 50% points on the rising and falling edges
rise time
fall time
bit time
pulse width
A periodic pulse waveform is one that repeats itself at a fixed interval.
True
False
A periodic digital waveform has a pulse width of 30μs and a period of 160μs. Determine the frequency and the duty cycle.
62.5 kHz, 18.75%
6.25 kHz, 18.75%
0.625 kHz, 18.75%
625 kHz, 18.75%
convert binary number (11011001) to decimal
216
217
218
219
convert fraction binary number (0.1101) to decimal
0.0625
0.25
0.5
0.8125
convert decimal (156) to binary
10011101
10011100
10011110
10011111
convert decimal fraction (11.3125) to binary
1011.0101
1011.0110
1011.1010
1011.0100
convert decimal (269) to hexadecimal
10A
10B
10C
10D
convert hex (F3B7) to binary
1111011110110111
1111001110110111
1111001111110111
1111001110100111
convert binary (10011011) to octal
233
133
463
433
The result of (1000 – 0111) is
1000
0001
0100
0010
The result of (11011 × 101) is equal to
10010111
11000111
10001111
10000111
The result of (1011.1) and (10.1) id equal to
11101.11
11100.11
11100.11
11000.11
The 2's complement of (00010100) is
11101100
11111100
11101000
11100100
The result of (DF)16 + (AC)16 is
8C
18C
8B
18B
The result of (7C39 – 37F2) =
4446
4447
4474
4464
express the decimal number (-30) as a binary
111110
011110
111100
011110
the BCD equivalent of (64.12)10 is
110100.001011
110110.001010
110100.011010
110100.001010
Find the BCD equivalent of the binary number 10101011.101 is
0001 0111 0011.0110
0010 0101
0001 0111 0001.0110
0010 0101
0001 0111 0001.0111
0010 0101
0001 0111 0001.0110
0110 0101
find the excess-3 code for the decimal number (2345)
0101011001111000
0101011101111000
0111011001111000
0101011001111010
Find the decimal equivalent of the excess-3 number 110010100011.01110101
970.40
970.43
970.41
970.42
convert binary (101110) to gray code
111101
111001
111011
110001
convert gray code (110101) into binary
100111
110110
100110
101110
An OR gate produces a HIGH output only when all of the inputs
are HIGH
True
False
An AND gate produces a HIGH on the output when any of the inputs is
HIGH
True
False
0,1,0,1
1,0,1,0
1,1,0,0
0,0,1,1
0,1,0,1
1,0,1,0
0,0,1,0
1,1,1,1
Apply Demorgan's theorem for the expression
The following boolean expression is
SOP
standard SOP
POS
standard POS
The following expression is
SOP
standard SOP
POS
standard POS
The following boolean expression is
SOP
standard SOP
POS
standard POS
Convert the following boolean expression into standard SOP form
The number of cells in a Karnaugh map For
three variables are
2
4
8
16
K-map is used for
logic minimization
expression maximization
summing of parity bits
logic gate creation
Simplify the expression using K-maps: F(A,B,C,D)=Σ (1,3,5,6,7,11,13,14)
Simplify the expression using K-maps: F(A,B,C) = Σ (1,3,5,6,7).
The sum and carry of full adder is
S = A ⊕ B ⊕ Cin
C = AB + (A⊕B)
True
False
A decoder converts n inputs to __________ outputs.
n
n2
2n
nn
Which of the following represents a number of output lines for a decoder with 4 input lines?
15
16
17
18
If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
2
m
n
2n
How many select lines would be required for an 8-line-to-1-line multiplexer?
2
3
4
8
X0
X1
X2
X3
When both inputs of a J-K flip-flop cycle J=0, K=0, the output will ___________
invalid
Change
Not change
Toggle
In S-R flip-flop, if S = 0, R=1 the output is said to be ___________
Set
Reset
Invalid
No change
How many input terminal is represented by T flip flop?
4
3
2
1
T flip flop
D flip flop
RS flip flop
Decoder
A basic memory storage element in a digital system is
flip flop
counter
multiplexer
encoder
How many natural states will there be in a 4-bit ripple counter?
4
8
16
32
A ripple counter’s speed is limited by the propagation delay of _____________
Each flip-flop
All flip-flops and gates
The flip-flops only with gates
Only circuit gates
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
12 ms
24 ms
48 ms
60 ms
An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
1
4
8
15
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
15 ns
30 ns
45 ns
60 ns
12.5 MHZ
15 MHZ
17.5 MHZ
20 MHZ
asynchronous counter
ring counter
synchronous counter
combinational circuit
10
3
4
5
N
2^(N)
2^(N-1)
2^(N)-1
UP-DOWN counter is a combination of ____________
Latches
Flip-flops
UP counter
Up counter & down counter
In 4-bit up-down counter, how many flip-flops are required?
2
3
4
5
Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.
2
3
4
5
The full form of SIPO is ___________
Serial-in Parallel-out
Parallel-in Serial-out
Serial-in Serial-out
Serial-In Peripheral-Out
How can parallel data be taken out of a shift register simultaneously?
Use the Q output of the first FF
Use the Q output of the last FF
Tie all of the Q outputs together
Use the Q output of each FF
The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________
01110
00001
00101
00110
With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
4 μs
40 μs
400 μs
40 ms
