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Digital electronics

Total questions: 68

Worksheet time: 1hrs 3mins

Name
Class
Date
1.

The time required for a pulse to go from LOW level to HIGH level is called

a)

rise time

b)

fall time

c)

bit time

d)

pulse width

2.

the time required for the transition from the HIGH level to LOW level is called

a)

rise time

b)

fall time

c)

bit time

d)

pulse width

3.
  • the measure of duration of the pulse and is often defined as the time interval between 50% points on the rising and falling edges

a)

rise time

b)

fall time

c)

bit time

d)

pulse width

4.

A periodic pulse waveform is one that repeats itself at a fixed interval.

a)

True

b)

False

5.

A periodic digital waveform has a pulse width of 30μs and a period of 160μs. Determine the frequency and the duty cycle.

a)

62.5 kHz, 18.75%

b)

6.25 kHz, 18.75%

c)

0.625 kHz, 18.75%

d)

625 kHz, 18.75%

6.

convert binary number (11011001) to decimal

a)

216

b)

217

c)

218

d)

219

7.

convert fraction binary number (0.1101) to decimal

a)

0.0625

b)

0.25

c)

0.5

d)

0.8125

8.

convert decimal (156) to binary

a)

10011101

b)

10011100

c)

10011110

d)

10011111

9.

convert decimal fraction (11.3125) to binary

a)

1011.0101

b)

1011.0110

c)

1011.1010

d)

1011.0100

10.

convert decimal (269) to hexadecimal

a)

10A

b)

10B

c)

10C

d)

10D

11.

convert hex (F3B7) to binary

a)

1111011110110111

b)

1111001110110111

c)

1111001111110111

d)

1111001110100111

12.

convert binary (10011011) to octal

a)

233

b)

133

c)

463

d)

433

13.

The result of (1000 – 0111) is

a)

1000

b)

0001

c)

0100

d)

0010

14.

The result of (11011 × 101) is equal to

a)

10010111

b)

11000111

c)

10001111

d)

10000111

15.

The result of (1011.1) and (10.1) id equal to

a)

11101.11

b)

11100.11

c)

11100.11

d)

11000.11

16.

The 2's complement of (00010100) is

a)

11101100

b)

11111100

c)

11101000

d)

11100100

17.

The result of (DF)16 + (AC)16 is

a)

8C

b)

18C

c)

8B

d)

18B

18.

The result of (7C39 – 37F2) =

a)

4446

b)

4447

c)

4474

d)

4464

19.

express the decimal number (-30) as a binary

a)

111110

b)

011110

c)

111100

d)

011110

20.

the BCD equivalent of (64.12)10 is

a)

110100.001011

b)

110110.001010

c)

110100.011010

d)

110100.001010

21.

Find the BCD equivalent of the binary number 10101011.101 is

a)

0001 0111 0011.0110

0010 0101

b)

0001 0111 0001.0110

0010 0101

c)

0001 0111 0001.0111

0010 0101

d)

0001 0111 0001.0110

0110 0101

22.

find the excess-3 code for the decimal number (2345)

a)

0101011001111000

b)

0101011101111000

c)

0111011001111000

d)

0101011001111010

23.

Find the decimal equivalent of the excess-3 number 110010100011.01110101

a)

970.40

b)

970.43

c)

970.41

d)

970.42

24.

convert binary (101110) to gray code

a)

111101

b)

111001

c)

111011

d)

110001

25.

convert gray code (110101) into binary

a)

100111

b)

110110

c)

100110

d)

101110

26.

An OR gate produces a HIGH output only when all of the inputs

are HIGH

a)

True

b)

False

27.

An AND gate produces a HIGH on the output when any of the inputs is

HIGH

a)

True

b)

False

28.
a)

0,1,0,1

b)

1,0,1,0

c)

1,1,0,0

d)

0,0,1,1

29.
a)

0,1,0,1

b)

1,0,1,0

c)

0,0,1,0

d)

1,1,1,1

30.

Apply Demorgan's theorem for the expression

a)

b)

c)

d)

31.

The following boolean expression is

a)

SOP

b)

standard SOP

c)

POS

d)

standard POS

32.

The following expression is

a)

SOP

b)

standard SOP

c)

POS

d)

standard POS

33.

The following boolean expression is

a)

SOP

b)

standard SOP

c)

POS

d)

standard POS

34.

Convert the following boolean expression into standard SOP form

a)

b)

c)

d)

35.

The number of cells in a Karnaugh map For

three variables are

a)

2

b)

4

c)

8

d)

16

36.

K-map is used for

a)

logic minimization

b)

expression maximization

c)

summing of parity bits

d)

logic gate creation

37.

Simplify the expression using K-maps: F(A,B,C,D)=Σ (1,3,5,6,7,11,13,14)

a)

b)

c)

d)

38.

Simplify the expression using K-maps: F(A,B,C) = Σ (1,3,5,6,7).

a)

b)

c)

d)

39.

The sum and carry of full adder is

S = A ⊕ B ⊕ Cin

C = AB + (A⊕B)

a)

True

b)

False

40.
a)

b)

c)

d)

41.
a)

b)

c)

d)

42.
a)

b)

c)

d)

43.

A decoder converts n inputs to __________ outputs.

a)

n

b)

n2

c)

2n

d)

nn

44.

Which of the following represents a number of output lines for a decoder with 4 input lines?

a)

15

b)

16

c)

17

d)

18

45.

If the number of n selected input lines is equal to 2^m then it requires _____ select lines.

a)

2

b)

m

c)

n

d)

2n

46.

How many select lines would be required for an 8-line-to-1-line multiplexer?

a)

2

b)

3

c)

4

d)

8

47.
a)

X0

b)

X1

c)

X2

d)

X3

48.

When both inputs of a J-K flip-flop cycle J=0, K=0, the output will ___________

a)

invalid

b)

Change

c)

Not change

d)

Toggle

49.

In S-R flip-flop, if S = 0, R=1 the output is said to be ___________

a)

Set

b)

Reset

c)

Invalid

d)

No change

50.

How many input terminal is represented by T flip flop?

a)

4

b)

3

c)

2

d)

1

51.
a)

T flip flop

b)

D flip flop

c)

RS flip flop

d)

Decoder

52.

A basic memory storage element in a digital system is

a)

flip flop

b)

counter

c)

multiplexer

d)

encoder

53.

How many natural states will there be in a 4-bit ripple counter?

a)

4

b)

8

c)

16

d)

32

54.

A ripple counter’s speed is limited by the propagation delay of _____________

a)

Each flip-flop

b)

All flip-flops and gates

c)

The flip-flops only with gates

d)

Only circuit gates

55.

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns

a)

12 ms

b)

24 ms

c)

48 ms

d)

60 ms

56.

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

a)

1

b)

4

c)

8

d)

15

57.

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________

a)

15 ns

b)

30 ns

c)

45 ns

d)

60 ns

58.
a)

12.5 MHZ

b)

15 MHZ

c)

17.5 MHZ

d)

20 MHZ

59.
a)

asynchronous counter

b)

ring counter

c)

synchronous counter

d)

combinational circuit

60.
a)

10

b)

3

c)

4

d)

5

61.
a)

N

b)

2^(N)

c)

2^(N-1)

d)

2^(N)-1

62.

UP-DOWN counter is a combination of ____________

a)

Latches

b)

Flip-flops

c)

UP counter

d)

Up counter & down counter

63.

In 4-bit up-down counter, how many flip-flops are required?

a)

2

b)

3

c)

4

d)

5

64.

Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.

a)

2

b)

3

c)

4

d)

5

65.

The full form of SIPO is ___________

a)

Serial-in Parallel-out

b)

Parallel-in Serial-out

c)

Serial-in Serial-out

d)

Serial-In Peripheral-Out

66.

How can parallel data be taken out of a shift register simultaneously?

a)

Use the Q output of the first FF

b)

Use the Q output of the last FF

c)

Tie all of the Q outputs together

d)

Use the Q output of each FF

67.

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

a)

01110

b)

00001

c)

00101

d)

00110

68.

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

a)

4 μs

b)

40 μs

c)

400 μs

d)

40 ms