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Multiple Choice Questions on HDL & Verilog

Total questions: 25

Worksheet time: 13mins

Name
Class
Date
1.

Which level of abstraction describes the functionality of a circuit?

a)

Gate Level

b)

Switch Level

c)

Architecture / Algorithm Level

d)

RTL Level

2.

Which HDL level describes the data flow of a circuit?

a)

Architecture Level

b)

RTL Level

c)

Gate Level

d)

Switch Level

3.

Which level focuses on the connectivity (structure) of a circuit?

a)

RTL Level

b)

Gate Level

c)

Algorithm Level

d)

Behavioral Level

4.

What is the primary reason for using HDL?

a)

Hardware Implementation

b)

Simulation and Design Exploration

c)

Manual Wiring

d)

None

5.

Which of the following is an advantage of HDL?

a)

More time-consuming

b)

Independent of fabrication technology

c)

Requires physical hardware

d)

Cannot verify functionality early

6.

In which year was Verilog HDL introduced?

a)

1984

b)

1990

c)

1989

d)

1995

7.

Who created the Verilog language?

a)

Phil Moorby

b)

John Doe

c)

Cadence Team

d)

IEEE Committee

8.

When did Verilog become public domain?

a)

1984

b)

1989

c)

1990

d)

1995

9.

Which organization standardized Verilog in 1995?

a)

IEEE

b)

Cadence

c)

Gateway

d)

OVI

10.

Which feature makes Verilog easy to learn?

a)

Similarity to Pascal

b)

Similarity to C

c)

Complicated Syntax

d)

No Libraries

11.

Which HDL allows mixed levels of abstraction in the same model?

a)

Verilog

b)

VHDL

c)

Assembly

d)

C++

12.

Which design methodology starts from top module and refines down?

a)

Top Down

b)

Bottom Up

c)

RTL

d)

Gate Level

13.

Which design methodology builds small blocks first and integrates later?

a)

Top Down

b)

Bottom Up

c)

RTL

d)

Behavioral

14.

What type of counter is a ripple counter?

a)

Synchronous

b)

Asynchronous

c)

Clock-Free

d)

Static

15.

Which flip-flop is used in a ripple counter?

a)

D Flip-Flop

b)

T Flip-Flop

c)

JK Flip-Flop

d)

SR Flip-Flop

16.

Which bit acts as LSB in ripple counter?

a)

First Flip-Flop

b)

Last Flip-Flop

c)

Middle Flip-Flop

d)

None

17.

In Verilog, what is the basic building block called?

a)

Cell

b)

Module

c)

Process

d)

Program

18.

Which Verilog module characteristic allows multiple modules in one file?

a)

Top-Down Design

b)

Multiple Definition Capability

c)

Nested Modules

d)

Behavioral Code

19.

Can module declarations be nested in Verilog?

a)

Yes

b)

No

c)

Sometimes

d)

Only for synthesis

20.

What does RTL stand for?

a)

Register Transfer Logic

b)

Rapid Timing Logic

c)

Real Time Logic

d)

Register Timing Level

21.

Which Verilog feature helps post-logic synthesis simulation?

a)

Rich Libraries from Vendors

b)

Nested Modules

c)

PLI

d)

Behavioral Description

22.

Which interface allows custom C code interaction in Verilog?

a)

VPI

b)

API

c)

PLI

d)

HDL Interface

23.

Which of the following is NOT an advantage of HDL?

a)

Abstract Level Design

b)

Reusable Across Technologies

c)

Needs Manual Wiring

d)

Early Verification

24.

Which year saw enhancements to Verilog for scalable designs?

a)

1989

b)

1995

c)

2001

d)

1990

25.

Which organization controlled Verilog after Cadence?

a)

IEEE

b)

OVI

c)

VHDL Consortium

d)

Open Source Group