wayground logo

Free Printable Worksheets

Font size

S
M
L
XL
Worksheets

CEA201_FA24_FE

Total questions: 50

Worksheet time: 4hrs 10mins

Name
Class
Date
1.

Choose the most four basic funtions of a computer

a)

Moving data, stroring data, processing data, controlling

b)

Supporting operating system, accessing hard disks, support network connections, supporting HDMI ports

c)

Reading disks, accessing network resources

d)

Reading data from keyboard, printing data to monitor, allowing network connections

2.

... refers to the operational units and their interconnections that realize the architectural specifications.

a)

Computer architecture

b)

Computer function

c)

Computer organization

d)

Instruction set architecture

3.

What is the most important function of the control unit (CU) ?

a)

It manages the order of running instructions

b)

It will read and process data from main memory

c)

It directs the operation of the other CPU components

d)

It will read instructions from main memory then decoding them

4.

The first generation of computers used ... for digital logic elements and memory

a)

Transistors

b)

Interated circuits

c)

Large-scale integration

d)

Vacumn Tubes

5.

What is Memory Address Register (MAR)?

a)

Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit

b)

Employed to hold temporarily the righthand instruction from a word in memory

c)

Contains the address in memory of the word to be written from or read into MBR

d)

Contains the address of the next instruction pair to be fetched from memory

6.

In the computer, what categories do external devices include (choose 3 correct answers)

a)

Human readable

b)

Communication

c)

Data Conversion

d)

Machine readable

7.

What is false about the Von Neuman architecture?

a)

Data and instructions are stored in a single read-write memory

b)

The contents of this memory are addressable by location, without regard to the type of data contained there

c)

Execution occurs in a sequential fashion (unless explicity modified) from one instruction to the next

d)

Data is stored in main memory and instructions are stored in cache memory

8.

What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?

a)

16 GB

b)

16 MB

c)

16 Gbits

d)

16 Mbits

9.

... interprets the instructions in memory and causes them to be executed

a)

Registers

b)

CPU interconnection

c)

ALU

d)

I/O Modules

e)

Control unit

10.

What is the correct order of memory access speed from fastest to lowest?

a)

Registers > Cache > RAM > SSD

b)

Cache > Registers > RAM > SSD

c)

Registers > Cache > SSD > RAM

d)

Cache > Registers > SSD > RAM

e)

All of the mentioned are wrong

11.

What is the most important characteristic of the Synchronous Bus?

a)

Data is transmitted at the same time

b)

The occurrence of one event on a bus follows and depends on the occurrence of a previous event

c)

The occurrence of events on the bus is determined by a clock

d)

No common clock signal controlling operation

12.

What is the special feature of Memory Cache?

a)

Allows faster access than DRAM memory

b)

Memory cache is outboard storage memory

c)

Allows faster access than CPU registers

d)

Fixed memory - Read Only Memory

e)

Has a larger capacity than HDD

13.

In direct mapping method from 256MB main memory with 512KB cache, what is the number of bits for the TAG element in the address?

a)

6

b)

7

c)

8

d)

9

14.

A byte addressable microprocessor has 24 bit address. What is the maximum capacity?

a)

4 MegaByte

b)

8 MegaByte

c)

16 MegaByte

d)

32 MegaByte

15.

In error correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?

a)

4

b)

5

c)

6

d)

7

16.

What is correct about increasing performance and endurance?

a)

Hard Disk - DRAM - NAND Flash -SRAM

b)

Hard Disk - NAND Flash- DRAM -SRAM

c)

NAND Flash - Hard Disk - SRAM - DRAM

d)

Hard Disk - DRAM - SRAM - NAND Flash

17.

With the hard disk data layout, the set of all the tracks in the same relative position on the platter, is called ...

a)

Cylinder

b)

Tracks

c)

Inter-track gap

d)

Sector

18.

Which RAID level uses striping technique with a minimum of 3 dsisks and provides fault tolerance through the use of parity bit?

a)

RAID 0

b)

RAID 1

c)

RAID 2

d)

RAID 3

19.

In terms of performance, what is the main advantage of a solid state driver over a magnetic disk?

a)

A solid state drive has faster access time, low latency, and higher reliability

b)

A solid state drive has larger capacity, lower power comsumption, and lower cost

c)

A solid state drive ha better compatibility, longer lifespan, and higher security

d)

A solid state drive has none of the mentioned advantages over a magnetic disk

20.

Consider the expression: NOT ( A + B ) = ?
Apply DeMorgan's Theorem to replace at "?"

a)

NOT A AND NOT B

b)

NOT A OR NOT B

c)

NOT A AND B

d)

A OR NOT B

21.

(1) An I/O module must recognize one unique address for each periphperal it controls.

  1. (2) I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.

  2. The statement (1) is ... and (2) is ...

a)

true, false

b)

true, true

c)

false, true

d)

false, false

22.

What is an interrupt vector?

a)

Part of memory which contains the addresses of interrupt handlers

b)

A signal an I/O module device sends to CPU

c)

A signal an I/O software sends to CPU

d)

None of the mentioned

23.

... : If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand

a)

Operand fetch

b)

Datta operation

c)

Operand store

d)

Operand address calculation

24.

What role does an Application Programming Interface (API) play in software development?

a)

It allows program access to hardware resources using high-level languages libraries

b)

It defines low-level machine instructions

c)

It provides a standard for binary portability

d)

It manages system resources for the operating system and machine language instructions

25.

What is the initial state of a process when it is admitted by the high-level scheduler, but not yet ready to execute?

a)

New

b)

Ready

c)

Running

d)

Halted

26.

Which of the following statements is incorrect about Translation Look-aside Buffer (TLB)?

a)

The use iof TLB eliminates the need for keeping a page table in memory

b)

TLB only mantains a subset of the entries stored in the full memory-based page table

c)

When there is a TLB miss system needs to access the page table

d)

A Translation Look-aside Buffer (TLB) is a memory cache thhat stores the recent translations of virtual memory to physical memory

27.

How does Boolean algebra contribute to the design of digital circuits?

a)

It simplifies the implenmentation of desired functions

b)

It helps in the analysis of economic data

c)

It facilitates the design of analog circuits

d)

It is primarily used for chemical engineering and physical engineering

28.

When both inputs are 1, what is the result of a NAND gate?

a)

0

b)

1

c)

2

d)

Undefined

e)

#NA

29.

What is the result of 10100101 XOR 11001001

a)

11101101

b)

10000001

c)

01101100

d)

10101100

30.

What is the result left rotate of 10110101 by 2 bit?

a)

01101011

b)

10101101

c)

01101101

d)

11010110

e)

11010100

31.

Why is it essential to use symbolic representation of machine instructions?

a)

It makes machine instructions more human-readable and understandable

b)

It reduces the overall complexity of computer systems and user programs

c)

It minimizes the need for memory storage for the user programs

d)

It enables fastest execution of high level language instructions

32.

What is the most important general categories of data that machine instructions operate on?

a)

Addresses, numbers, characters, and logical data

b)

Texts, images, and audio

c)

Variables, functions, and arrays

d)

Instructions, control signals, and registers

33.

What is a branch instruction?

a)

The instruction that are used to divide a program into multiple subprograms

b)

The instruction that have as one of its operands the address of the next instruction to be executed

c)

The instruction that are used to pause the program

d)

The instruction that are used to return to the beginning of the program

34.

The effective address of Register indirect addressing mode is ...

a)

EA = R

b)

EA = (R)

c)

EA = (R) + A

d)

EA = (R) + (A)

35.

Which of the following PDP series computers is known for its use of 12-bit instructions and a single general-purpose registerm, the accumulator?

a)

PDP-8

b)

PDP-10

c)

PDP=11

d)

PDP-6

36.

What is the main different between x86 and ARM instruction formats?

a)

x86 instructions are variable in length, while ARM instructions are fixed

b)

x86 instructions are fixed in length, while ARM instructions are fixed are variable

c)

Both x86 and ARM instructions are fixed in length

d)

Both x86 and ARM instructions are variable in length

37.

What is the primary purpose of the "Fetch instruction" phase in the operation of a processor?

a)

To read an instruction from memory

b)

To interpret the instruction

c)

To perform arithmetic operations on data

d)

To write data to memory

38.

Control and status registers are used by which entities to control the operation of the processor?

a)

Privileged, operating system programs

b)

Machine or assembly language programmers

c)

External I/O devices

d)

Main memory modules

39.

What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?

a)

PC is not used in the fetch phase, and its role is limited to tracking the number of instructions executed bt the CPU

b)

PC in the fetch phase holds the memory address of the next instruction to be fetched and executed

c)

PC is responsible for executing instructions and has no specific role during the fetch phase

d)

PC is only relevant in multi-core processors and does not contribute to the fetch phase of the instruction cycle in single-core systems

40.

Which of the following statement is correct in the context of Instruciton Pipelining?

a)

Instruciton Pipelining reduces the efficiency of instruction execution by introducing delays and dependencies between instructions

b)

Instruction Pipelining is only effictive for specific type of instructions are has no impact on the overall efficiency of instruction execution

c)

Instruciton Pipelining enhances efficiency by enabling simultaneous execution of multiple instructions in different stages, boosting overall throughput

d)

Instruciton Pipelining improves efficiency by processing multiple instructions simultaneously, reducing execution time. However, it can face challanges like hazards, introducing delays and impacting overall performance

41.

Which statement is incorrect about RISC and CISC architecture?

a)

CISC architecture is more convenient for programmers than RISC architecture

b)

CISC architecture has more operands in a instruction compared to RISC architecture

c)

CISC architecture has a more flexoble instruction set than RISC architecture

d)

CISC architecture requires more general-purpose registers than RISC architecture

42.

What is one of the advantages of using a register file in computer architecture

a)

Reduction in memory accesses, saving time

b)

More efficient use of space due to dynamic adaptation

c)

Efficient handling of both local and global variables

d)

Easier management of cache residency

43.

How does pipelining in a RISC architecture handle branch instruction?

a)

By using NOOP instruction inserted bt the compiler or assembler

b)

By elimitnating branch instructions from the instruction stream

c)

By executing branch instructions in a separate pipeline

d)

By delaying all instructions until branch instructions are executed

44.

What is the benefit of using a superscalar organization over a scalar organization?

a)

It increases the instruction throughput and improves the performance

b)

It reduces the power consumption and the heat dissipation

c)

It simplifies the instruction set and compiler design

d)

All of the mentioned

e)

None of the mentioned

45.

What does the term "instruction-level parallelism" refer to in computer architecture?

a)

The degree to which instructions in a program can be executed in parallel

b)

The number of processor cores in a multi-core CPU with multiple resources

c)

The complexity of the instruction set architecture

d)

The lenght of an instruction cycle with high level programming language

46.

"Multiple processors share a single memory or pool of memory by means of a shared bus or other interconnection mechanism; a distinguishing feature is that the memory access time to any region of memory is approximately the same for each processor". Which concept does the statement belong to?

a)

Symmetric multiprocessor (SMP)

b)

Nonuniform memory access (NUMA)

c)

Cluster

d)

Single instruction, multiple data (SIMD)

47.

Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid?

a)

Write through

b)

Write back

c)

Write around

d)

No write allocate

48.

What is one advantage of Nonuniform Memory Access (NUMA) over Uniform Memory Access (UMA)?

a)

NUMA provides each processor with its own local memory, reducing memory access times

b)

NUMA allows all processors to access the same memory location simultaneously

c)

NUMA is easier to implenment than UMA

d)

NUMA provides limited memory capacity

49.

Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f=0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be ...

a)

307%

b)

297%

c)

317%

d)

327%

50.

What is the most common mapping technique used in cache memory in modern computers?

a)

Direct Mapping

b)

Fully Associative

c)

Set Associative

d)

None of the mentioned