Worksheetsgroup 5
Total questions: 10
Worksheet time: 5mins
What is the main advantage of a superscalar processor?
A. Executes one instruction per cycle
B. Executes multiple instructions in a single cycle
C. Increases cache size
D. Reduces instruction length
2. Which technique helps avoid write-after-read and write-after-write hazards?
A. Branch prediction
B. Instruction pipelining
C. Register renaming
D. Microcode sequencing
3. What is the function of the Branch Target Buffer (BTB)?
A. Stores data values for registers
B. Caches addresses of recent branch targets
C. Tracks reorder buffer entries
D. Manages cache eviction policy
4. Out-of-order execution improves performance by:
A. Reducing the number of pipelines
B. Executing instructions strictly in program order
C. Executing ready instructions earlier
D. Delaying all instructions until branch resolution
5. In Intel microarchitecture, complex instructions are handled by:
A. L1 data cache
B. Instruction queue
C. Micro-op schedulers
D. Microcode ROM
6. Which of the following is NOT a type of branch predicted by the Branch Prediction Unit?
A. Conditional branch
B. Indirect branch
C. Register spill
D. Function return
What does the Instruction Decode Unit produce after decoding?
A. Control signals
B. Micro-operations (micro-ops)
C. Cache blocks
D. Memory addresses
8. The Reorder Buffer (ROB) is used to:
A. Schedule floating-point instructions
B. Ensure correct program order during commit
C. Replace branch prediction
D. Increase memory bandwidth
In superscalar architecture, instruction-level parallelism is limited by:
A. Cache line size
B. Clock frequency
C. Dependencies between instructions
D. Number of CPU cores
The rename stage maps architectural registers to:
A. Control signals
B. Memory addresses
C. Physical registers
D. Instruction queues
