WorksheetsPCB Design Situational-Based MCQs - Basic to Intermediate
Total questions: 40
Worksheet time: 20mins
A customer reports EMI issues in your design. What’s your first corrective action?
Increase silkscreen size
Add decoupling capacitors near high-speed ICs
Remove ground plane
Increase trace width
During layout, your high-speed differential pair traces are not length-matched. What issue may occur?
Component misplacement
Differential signal skew
Better signal quality
Increased power efficiency
Your PCB fails during high-current operation due to track heating. What must be adjusted?
Solder mask thickness
Copper trace width
Silkscreen font size
Drill hole size
Crosstalk is observed between parallel traces. How can this be minimized?
Increase trace width
Reduce layer count
Route signals orthogonally on adjacent layers
Add silkscreen boundaries
A multilayer PCB shows poor power distribution. What layout technique improves this?
Use larger vias
Use solid power planes
Reduce trace length
Increase silkscreen contrast
Your Gerber output doesn’t show the drill holes. What likely went wrong?
Drill layer not generated/exported
Copper layers are missing
Text overlap occurred
You skipped netlist import
Your BGA layout causes open pins post-assembly. What can fix this in layout?
Use via-in-pad with appropriate capping
Rotate the BGA
Remove the BGA
Decrease solder mask opening
A via used for signal routing is isolated on one layer. What’s the cause?
Wrong net assignment
Missing solder mask
Improper drill diameter
Missing silkscreen
Your PCB’s thermal performance is poor around a voltage regulator. What layout fix is best?
Increase copper pour area around it
Add more vias under the IC
Add heatsinks directly to trace
Use multiple footprints
Which layout strategy is best to avoid ground loop issues?
Use multiple ground planes
Use star grounding technique
Use thinner traces
Add multiple decoupling caps
An LDO regulator’s output is unstable. You discover a layout issue. What’s most likely?
Long trace between regulator and load
Thicker copper layer
Better silkscreen contrast
Wrong Gerber file
A power trace is routed under a sensitive analog signal line. What issue can arise?
Reduced resistance
Crosstalk/Noise interference
Improved heat dissipation
Enhanced resolution
You forgot to include test points in your PCB design. What’s the consequence?
Increased impedance
Difficulty in post-manufacturing validation
Reduced footprint
More stable signal
When designing a 4-layer PCB, how should signal and ground layers be arranged for best performance?
Signal-Ground-Signal-Power
Power-Signal-Ground-Signal
Signal-Ground-Power-Ground
Signal-Power-Signal-Ground
You get pad-to-via spacing DRC errors in high-density areas. What layout method can help?
Reduce board size
Use microvias or blind vias
Add more test points
Decrease component size only
A PCB’s silkscreen includes component values but overlaps pads. What’s the correct practice?
Increase font size
Ignore overlaps
Move silkscreen outside pad boundary
Remove all silkscreen
After routing, some ground vias are missing connections to the ground plane. What caused this?
Missing drill file
Wrong via net assignment
Inverted silkscreen
Incorrect soldermask
Your PCB passes simulations but fails in thermal testing. What design aspect was likely missed?
Use of thermally conductive paths
Increased trace width
Better net labeling
Increased soldermask thickness
A client demands faster prototyping. Which layout practice supports this goal?
Strictly use through-hole components
Follow DFM guidelines for standard fab
Use high copper weight
Avoid copper pours
While using autorouter, your differential pair ends up on different layers. What’s the impact?
Higher impedance
Lower EMI
No impact
Accurate signal transmission
You notice the silkscreen text overlaps with the pad area in your PCB layout. What should you do?
Proceed with fabrication
Shift the component slightly
Remove the silkscreen from pad areas
Increase pad size
A beginner designs a PCB without any ground plane. What is the likely issue?
Signal distortion
Larger board size
Component shortage
Wrong Gerber output
You accidentally placed a trace too close to a high-current track. What may result?
Trace melting
No issue
EMI interference
Better performance
You designed a board with missing via connections in the layout. What will likely happen?
Reduced board cost
Open circuits during operation
Faster signal speed
Lower power consumption
A trace width of 5 mil is selected for a 5A current. What is the risk?
Over-voltage
Trace overheat and failure
Increased reliability
No risk
You forgot to define net classes for high-speed signals. What does this affect?
Trace color
Layer stacking
Controlled impedance
Bill of materials
You’ve used sharp 90° corners in your trace routing. What is a common consequence?
Reduced trace resistance
Shorter path
Impedance discontinuity and signal reflection
Lower board cost
The footprint used for a component is smaller than the actual part. What happens during assembly?
Better thermal dissipation
Proper soldering
Misalignment or mounting failure
Cost reduction
You notice all silkscreen markings are missing in the output. What layer is likely omitted during export?
Top copper
Top paste
Top overlay
Drill
You designed a board with a mirrored top layer. What could go wrong?
Cheaper PCB
Silkscreen appears inverted
Correct layout
No changes
A track breaks after etching. What is a likely cause?
Incorrect grid
Low etchant temperature
Trace too thin
Too much solder
You forgot to add fiducials in a board intended for automated assembly. What is affected?
Power quality
Signal clarity
Component placement accuracy
Routing speed
A layout fails DRC due to annular ring issues. What parameter must you adjust?
Pad size
Hole drill size
Trace clearance
Copper pour area
A decoupling capacitor is placed far from the IC it supports. What’s the likely result?
Reduced signal speed
Increased EMI
Effective power filtering
Better thermal performance
You used the wrong via drill size for power connections. What happens?
Lower trace impedance
Reduced reliability
Enhanced connectivity
Higher manufacturing yield
You get a short between power and ground in the layout. What's the best debugging step?
Increase trace width
Review copper pours and nets
Re-export Gerber files
Change drill sizes
You notice multiple grounds are not interconnected. What did you likely forget?
Ferrite bead
Via stitching
Mounting holes
Test points
Which is a common spacing standard for track clearance in basic PCB layouts?
0.1 mm
10 mil
2.5 mm
0.001 inch
A PCB designed without mounting holes may result in:
Better signal speed
Difficult mechanical integration
Higher EMI tolerance
Lower assembly time
You exported a Gerber file without solder mask layers. What is the result?
Faster etching
Exposed copper areas
Lower PCB cost
Higher component accuracy
