WorksheetsComputer Architecture Quiz
Total questions: 20
Worksheet time: 7mins
What is the minimum time delay present between the initiations of two separate, independent memory operations known as?
Cycle Time
Latency Time
Access Time
Transfer Rate
In Register Indirect addressing mode, the operand is:
The register itself
The content of the register
The memory location pointed to by the register
The instruction itself
The program counter (PC) is updated during:
Decode phase
Fetch phase
Execute phase
Memory write-back
In a CPU datapath, the ALU receives inputs typically from:
Instruction register and program counter
Memory and cache
Register file outputs
Control unit directly
Which of the following is NOT part of a basic datapath?
Program Counter (PC)
ALU
Register File
Instruction Decoder
CPU execution time is given by:
Instruction Count × CPI × Clock Cycle Time
Instruction Count × Clock Rate × CPI
Clock Rate ÷ CPI
Instruction Count ÷ Clock Rate
A program requires 10⁹ instructions to execute. The processor has a clock rate of 2 GHz and average CPI = 2. The execution time is:
0.5 sec
1 sec
2 sec
4 sec
A processor delivers MIPS = 200. If it executes 10⁹ instructions, how much time is taken?
2 sec
5 sec
10 sec
20 sec
A supercomputer achieves 500 GFLOPS. If a program requires 2 × 10¹² floating-point operations, the execution time is:
2 sec
4 sec
5 sec
10 sec
If an 8-bit signed integer uses 2's complement representation, what is the range?
-255 to +255
-128 to +127
-127 to +128
0 to 255
In IEEE-754 single precision (32-bit), how many bits are used for exponent?
23
8
9
10
What is the correct sequence of phases in the instruction cycle?
Fetch → Decode → Execute → Store
Decode → Fetch → Execute → Store
Execute → Fetch → Decode → Store
Fetch → Execute → Decode → Store
If a CPU operates at 2 GHz and fetches one instruction per cycle, how many instructions can it fetch per second?
1 billion
2 billion
1 Million
2 Million
In double precision format, the size of the mantissa is (a) bits
Given two machines: Machine A: Clock rate = 3 GHz, CPI = 2 Machine B: Clock rate = 2 GHz, CPI = 1 Which machine has better performance assuming equal instruction counts?
Machine A
Machine B
Both same
Cannot determine
Which of the following is true about Modified Booth's algorithm?
It reduces the number of partial products by encoding three bits at a time
It increases the number of partial products compared to Booth's algorithm
It cannot handle negative numbers
It is slower than simple binary multiplication
Which category of instruction set focuses on minimizing the number of instructions per program by using complex instructions?
RISC (Reduced Instruction Set Computer)
CISC (Complex Instruction Set Computer)
VLIW (Very Long Instruction Word)
SISD (Single Instruction Single Data)
Which of the following techniques can improve the effective CPI of a processor?
Increasing clock frequency without changing CPI
Using pipelining and parallelism to reduce CPI
Increasing instruction count
Using longer instruction formats
If a CPU's clock rate is doubled but the CPI also doubles, the CPU execution time will:
Decrease by half
Increase by two times
Remain the same
Decrease by four times
What is the decimal equivalent of IEEE-754 single precision value: 0 10000001 01000000000000000000000
5.0
10.0
2.5
20.0
