Worksheets20EC204 Digital System Design -Surprize Quiz I
Total questions: 10
Worksheet time: 5mins
Which of the following logic families is most widely used in integrated circuits due to its reliability and speed?
DTL
TTL
ECL
CMOS
What is the typical noise margin for a CMOS gate?
0.1 V
0.3 V
1.0 V
2.5 V
Which of the following memory types can be electrically erased and reprogrammed multiple times?
PROM
EPROM
ROM
SRAM
Which of the following is NOT a type of PLD (Programmable Logic Device ?
GAL
FPGA
EEPROM
CPLD
A system designer wants to reduce the boot-up time of an FPGA-based system. Which configuration memory type should be avoided?
Flash
EEPROM
SRAM
Antifuse
When implementing a state machine on a CPLD, what characteristic must be considered for predictable timing?
LUT size
Propagation delay
Power
consumption
Analog interface
A TTL gate has a HIGH-level output voltage of 3.5V and LOW-level output voltage of 0.2V. The TTL input HIGH voltage minimum is 2.0V and LOW voltage maximum is 0.8V. Calculate the HIGH-level noise margin.
1.5V
2.0V
3.5V
0.2V
If a TTL gate output can drive 10 TTL inputs, what is its fan-out?
1
10
100
5
It is observed that the LOW-level noise margin of a TTL gate is 0.6V. If the input LOW voltage max is 0.8V, what is the output LOW voltage maximum?
1.4 V
0.2V
0.8V
0.6V
In FPGA design, what is the role of ‘place and route?
Writing HDL code
Assigning logic
elements
Debugging
the design
Simulating the
design behavior
