WorksheetsCAO M3
Total questions: 20
Worksheet time: 10mins
Which technique is used to increase ILP?
Branch prediction
Instruction scheduling
Loop unrolling Loop unrolling
All of the above
Data hazards that limit ILP include:
RAW, WAR, WAW
Only RAW
Only WAR
Control hazards
Which of the following is NOT a type of dependency in ILP?
Control dependencyControl dependency
Structural dependency
Data dependency
Thread dependency
Pipeline stalls due to branch instructions are caused by:
Control hazards
Data hazards
Structural hazards
None
Loop unrolling is done to:
Reduce number of loop iterations
Reduce branch penalty
Increase available parallelism
All of the above
Software pipelining is a technique where:
Loops are executed sequentially
Different iterations of loop are overlapped
Hazards are ignored
Instructions are reordered randomly
Register renaming helps to avoid:
RAW hazards
WAW and WAR hazards
Structural hazards
Control hazards
Instruction scheduling at compile-time cannot handle:
Known latencies
Variable memory latencies
Loop unrolling
Static reordering
A limitation of compiler-based ILP techniques is:
They cannot detect hazards
They rely on predictable runtime behavior
They are slower than hardware scheduling
They do not use registers
Dynamic scheduling is performed by:
Compiler
Hardware at runtime
Operating system
Programmer manually
The main advantage of dynamic scheduling is:
Handling unpredictable latencies
Lower hardware cost
Reduced ILP
Slower execution
Tomasulo’s algorithm uses:
Static scheduling
Scoreboarding
Reservation stations
Instruction replay
Dynamic scheduling can introduce:
Deadlocks
Pipeline stalls
Increased hardware complexity
All of the above
Which of the following limits ILP?
Control dependencies
Data dependencies
Memory aliasing
All of the above
Multithreading improves performance by:
Hiding memory latency by switching threads
Increasing single-thread speed
Reducing hardware
Eliminating cache
Simultaneous multithreading (SMT) differs from coarse-grained multithreading because:
SMT runs multiple threads in same cycle
Coarse-grained switches only on stalls
SMT increases ILP and TLP together
All of the above
Chip Multiprocessing (CMP) is also called:
Multiprogramming
Multicore
Multiprocessing with multiple chips
None
In shared memory systems, processors communicate via:
Message passing
Shared variables in memory
Network packets
None
Scalability of multicore systems depends on:
Synchronization overhead
Communication cost
Parallel fraction of workload
All of the above
Static scheduling works well when:
Memory access times are highly predictable
Memory latencies are random
Branch mispredictions are frequent
Cache misses dominate runtime
