WorksheetsCPU Architecture Quiz
Total questions: 25
Worksheet time: 13mins
What is the primary function of the Program Counter (PC)?
To store the result of arithmetic operations
To hold the address of the next instruction to be executed
To store the current instruction being processed
To control the timing of the CPU clock
Which component is responsible for performing arithmetic and logical operations?
Control Unit
Memory Address Register
Arithmetic Logic Unit (ALU)
Current Instruction Register
What does the Memory Data Register (MDR) store?
The address of data in memory
The actual data being transferred to or from memory
The current instruction being executed
The result of the last calculation
What is the correct sequence during the fetch phase?
PC → MAR → Memory → MDR → CIR
PC → CIR → MAR → Memory → MDR
MAR → PC → Memory → CIR → MDR
Memory → MAR → PC → MDR → CIR
Which bus carries the address of the memory location to be accessed?
Data bus
Control bus
Address bus
System bus
What role does the Control Unit play in the fetch-decode-execute cycle?
It performs all arithmetic calculations
It orchestrates and coordinates all operations by sending control signals
It stores all the program instructions
It only manages the cache memory
When does memory respond with the requested instruction during fetch?
Immediately when the PC is incremented
After receiving the address from MAR via the address bus
Only during the execute phase
Before the Control Unit sends any signals
Which bus is active when the Control Unit sends a 'read' signal to memory?
Address bus only
Data bus only
Control bus
All buses simultaneously
What happens during the decode phase of the FDE cycle?
The instruction is fetched from memory
The instruction is broken down and interpreted by the Control Unit
Arithmetic operations are performed
Results are stored back in memory
In which direction does data typically flow on the data bus during the fetch phase?
CPU to memory only
Memory to CPU only
Bidirectional simultaneously
Data bus is not used during fetch
What must happen in memory when the MAR contains a specific address?
Memory automatically sends all stored data
Memory waits for further instructions from the ALU
Memory locates and prepares the data at that address for transfer
Memory clears the address location
Which register holds the instruction currently being decoded and executed?
Program Counter (PC)
Memory Address Register (MAR)
Current Instruction Register (CIR)
Accumulator (ACC)
What is the correct timing for when the Program Counter increments?
Before the fetch phase begins
During or after the fetch phase, before decode
Only during the execute phase
After the execute phase is complete
How does the Control Unit know whether to send a 'read' or 'write' signal to memory?
It always sends both signals
It depends on the type of instruction being processed
Memory decides automatically
The ALU determines this
During the execute phase, if an ADD instruction needs data from memory, what sequence occurs?
ALU directly accesses memory
PC sends the address to memory
MAR holds data address, memory responds via MDR, ALU processes
CIR fetches the data automatically
Which factor would have the GREATEST impact on CPU performance for single-threaded applications?
Number of cores
Cache size
Clock speed
Bus width
What is the main advantage of pipelining in a processor?
It reduces power consumption
It allows multiple instructions to be processed simultaneously at different stages
It increases the size of the cache
It simplifies the instruction set
In Von Neumann architecture, where are both instructions and data stored?
In separate memory locations
In the same memory space
Instructions in ROM, data in RAM
Instructions in cache, data in main memory
What is a key characteristic of RISC processors compared to CISC processors?
They have more complex instructions
They have fewer, simpler instructions
They consume more power
They have smaller caches
What is the primary advantage of having multiple cores in a processor?
Higher clock speeds
Larger cache memory
Ability to execute multiple processes simultaneously
Reduced power consumption
How does cache memory improve CPU performance?
By increasing the clock speed
By storing frequently accessed data closer to the CPU
By adding more processing cores
By simplifying the instruction set
What is the main difference between Harvard and Von Neumann architecture?
Harvard has separate memory for instructions and data
Harvard processors are always faster
Von Neumann architecture has more registers
Harvard architecture uses RISC instructions only
Which buses are typically active during a complete fetch operation?
Address bus only
Address bus and data bus
Control bus and data bus only
All three buses are always active
What determines which specific location in memory is accessed during fetch?
The current instruction in CIR
The address stored in the Program Counter
A random memory location
The last result from the ALU
Which of the following best describes a GPU's primary advantage over a CPU for certain tasks?
Higher clock speeds
More cache memory
Ability to perform many simple operations in parallel
More complex instruction sets
