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WorksheetsComputer Organization: Memory Systems MCQs
Total questions: 30
Worksheet time: 15mins
“Locality of Reference” is related to:
Register
Cache
Primary Memory
Magnetic Tape
Expand CAM:
Cache Access Memory
Call Access Mode
Content Addressable Memory
Cache Access Module
Associative Memory is like:
Primary Memory
Secondary Memory
Cache Memory
Auxiliary Memory
In the Memory Hierarchy (Registers → Tape), capacity:
Decreases
Increases
Constant
Random
In the Memory Hierarchy (Registers → Tape), cost per bit:
Decreases
Increases
Constant
Random
Memory with least capacity:
Register
Cache
Primary Memory
Magnetic Tape
Memory with maximum access time:
Register
Cache
Primary Memory
Magnetic Tape
Static RAM consists of:
Capacitors
Internal Flip-Flops
Internal Caches
Filters
Dynamic RAM consists of:
Capacitors
Internal Flip-Flops
Internal Caches
Filters
Bootstrap loader resides in:
RAM
ROM
Any memory
CPU
Both cache and main memory updated on write operation is:
Write-back
Write-through
Associative
TLB
Only cache updated on write operation is:
Write-back
Write-through
Associative
Direct
Replacing block not used for longest period is:
FIFO
LRU
MRU
LFU
Memory accessed sequentially is:
Register
Cache
Primary Memory
Magnetic Tape
Refreshing is required for:
All RAMs
Only DRAMs
Only SRAMs
Both SRAMs and DRAMs
Main memory technology is based on:
Semiconductor ICs
Magnetic Tape
Optical Memory
Disk Storage
Two or more programs in memory at same time:
Uni-programming
Multiprogramming
Multitasking
Batch processing
Cache is used to:
Increase memory size
Increase processing speed
Match CPU-memory speed
Store data permanently
Cache mapping technique not used is:
Direct mapping
Associative mapping
Test-associative mapping
Set-associative mapping
In four-way set associative cache, number of tags is:
One
Two
Four
Eight
Fastest mapping technique is:
Direct mapping
Associative mapping
Set-associative mapping
Test-associative mapping
DMA stands for:
Direct Memory Access
Dynamic Memory Access
Direct Machine Access
Data Memory Access
I/O technique with least CPU involvement:
Programmed I/O
Interrupt I/O
DMA
Polling
Interrupt latency means:
Speed of interrupt
Delay between request and ISR start
Frequency of interrupts
CPU speed
Pipelining increases:
CPI
Throughput
Latency
Cost
Pipeline hazards are:
Data, Structural, Control
CPU, Memory, I/O
Bus, Address, Data
Read, Write, Execute
Floating point representation uses:
Sign and Magnitude
Mantissa and Exponent
2’s Complement
Octal form
Belady’s anomaly does not occur in:
FIFO
LRU
MRU
LFU
Cache transfers between CPU and cache occur in units of:
Word
Block
Byte
Line
DMA controller communicates directly with:
CPU
Main Memory
Cache
I/O Interface
