WorksheetsSystem Verilog Worksheet Wipro
Total questions: 30
Worksheet time: 15mins
What is the default value of an uninitialized wire in System Verilog?
0
1
x (unknown)
z (high impedance)
In System Verilog, what type of assignments can be made to reg variables?
Only continuous assignments
Only procedural assignments
Both continuous and procedural assignments
Neither continuous nor procedural assignments
The error in the code is : int a, b; initial begin forever begin a = a + 1; b = b + 1; end end
a and b can overflow as it is an infinite loop
simulation may not advance since “forever” does not have timing control
A “forever” block can never be a part of initial block.
No error.
What is the default size of a reg variable in SystemVerilog?
8 bits
16 bits
32 bits
1 bit
What is the precision of shortreal data type?
32-bit single precision
64-bit double precision
16-bit half precision
128-bit quad precision
What happens when you assign a shorter string to a longer string variable?
Compilation error occurs
The string is padded with null characters
The string is truncated
The string variable resizes automatically
Which of the following is a valid use of void?
void my_var;
function void display_msg();
void array[10];
parameter void PARAM = 5;
Which syntax correctly defines an enumerated type with typedef?
typedef enum {RED, GREEN, BLUE} color_t;
enum typedef {RED, GREEN, BLUE} color_t;
typedef {RED, GREEN, BLUE} enum color_t;
enum color_t {RED, GREEN, BLUE} typedef;
How do you declare a dynamic array in SystemVerilog?
int arr[10];
int arr[];
int arr[*];
int arr[$];
Which of the following are true with respect to arrays?
Dynamic arrays are useful for contagious collection of variables.
Associative arrays can be used if the size of array is not known
dynamic arrays can be resized after allocating the size.
All of these.
Which operator is used for non-blocking assignments?
=
<=
==
===
What is the difference between packed and unpacked structures?
Packed structures use more memory
Packed structures are stored as contiguous bits
Packed structures are slower
There is no difference
How do you increase the size of dynamic array by retaining its old values?
d_array =new[10]d_array;
d_array= new[10]
d_array=new[5,10]
none of these.
What is the key difference between while and do-while loops?
while is faster than do-while
do-while executes at least once
while supports break statements
do-while doesn't support continue
What does the continue statement do in a loop?
Exits the loop completely
Skips remaining statements and goes to next iteration
Pauses the loop execution
Restarts the loop from beginning
What is the difference between unique-if and priority-if?
priority-if allows multiple true conditions
unique-if allows multiple true conditions
priority-if checks conditions in order and stops at first true
There is no difference
How do you trigger an event in SystemVerilog?
event.trigger()
->event
trigger(event)
event->trigger
How many return values can a function have?
None
One
Multiple
Unlimited
What does fork-join_any do?
Waits for all threads to complete
Waits for any one thread to complete
Executes threads sequentially
Kills all threads after first completion
The difference between Device under Test and Device under Verification is:
Device under Test is the actual hardware being tested, while Device under Verification is the model used for verification.
Device under Test is the simulation model, while Device under Verification is the physical device.
Device under Test and Device under Verification are always the same entity.
Device under Test is used for software testing, while Device under Verification is used for hardware testing.
The code given below: module argument_passing; int x,y,z;//function to add two integer numbers. function int sum(ref int x,y); x = x+y; return x+y; endfunction This is an example of
argument pass by value
argument pass by reference
argument pass by name
argument pass by position
Arrange the following in order: 1) Generate stimulus 2) Apply stimulus to the DUT 3) Check for correctness 4) Capture the response 5) Measure progress against the overall verification goals
1,2,3,4,5
1,2,4,3,5
1,4,2,3,5
2,1,3,4,5
File extension of system Verilog is
.svl
.svd
.sv
.svs
Which is not a behavioural data type?
time
real
integer
event
What does the continue statement do in a loop?
Exits the loop completely
Skips remaining statements and goes to next iteration
Pauses the loop execution
Restarts the loop from beginning.
Which of the following statement is true regarding priority if and unique if?
In unique if, there will be an error, if more than one condition is true.
In unique if, if no condition is true, there will be an error.
In case of priority if, if no condition is true, there will be an error.
All of these.
What is the key characteristic of a union in SystemVerilog?
All members have separate memory locations
All members share the same memory location
Members are accessed sequentially
Members must be of the same data type
When should non-blocking assignments be used?
In combinational logic
In sequential logic
In continuous assignments
In function definitions
When is the void data type typically used in SystemVerilog?
For variable declarations
For function return types that return nothing
For array indexing
For parameter declarations
What is the default value of the first enumerated constant if not explicitly specified
0
1
X
z
