WorksheetsComputer Architecture MCQ (Worksheet Extraction)
Total questions: 100
Worksheet time: 50mins
Who developed the basic architecture of computer?
Blaise Pascal
Charles Babbage
John Von Neumann
None of the above
Which of the following is not considered as a peripheral device?
CPU
Keyboard
Monitor
All of the above
Which of the following computer memory is fastest?
Register
Hard disk
RAM
None of the above
Which of the following operations is/are performed by the ALU?
Data manipulation
Exponential
Square root
All of the above
Which of the following format is used to store data?
Decimal
Octal
BCD
Hexadecimal
Which of the following memory of the computer is used to speed up the computer processing?
Cache memory
RAM
ROM
none of the above
Computer address bus is -
Multidirectional
Bidirectional
Unidirectional
None of the above
Which of the following circuit is used to store one bit of data?
Flip Flop
Decoder
Encoder
Register
Which of the following is a way in which the components of a computer are connected to each other?
Computer parts
Computer architecture
Computer hardware
None of the above
The address in the main memory is known as –
Logical address
Physical address
Memory address
None of the above
Subtraction in computers is carried out by –
1's complement
2's complement
3's complement
9's complement
Which of the following memory unit communicates directly with the CPU?
Auxiliary memory
Main memory
Secondary memory
None of the above
The collection of 8-bits is called as -,
Byte
Nibble
Word
Record
Which of the following is a group of bits that tells the computer to perform a particular operation?
Accumulator
Register
Instruction code
None of the above
Where is the document temporarily stored during working on a document on PC?
ROM
CPU
RAM
Flash memory
Where is the decoded instruction stored?
Registers
MDR
PC
IR
The status bit is also called as –
Unsigned bit
Signed bit
Flag bit
None of the above
Which of the following register can interact with the secondary storage?
PC
MAR
MDR
IR
Which of the following is not considered as a peripheral device?
CPU
Keyboard
Monitor
All of the above
Which of the following is an essential data transfer technique?
MMA
DMA
CAD
CAM
RISC stands for –
Reduce Instruction Set Computer
Risk Instruction Sequential Compilation
Risk Instruction Source Compiler
None of the above
In which of the following term the performance of cache memory is measured?
Chat ratio
Hit ratio
Copy ratio
Data ratio
Which of the following is the function of the control unit in the CPU?
It stores program instruction
It decodes program instruction
It performs logic operations
None of the above
Which of the following computer register collects the result of computation?
Accumulator
Instruction Pointer
Storage register
None of the above
Which of the following building block can be used to implement any combinational logic circuit?
AND
OR
NAND
None of the above
What does a computer bus line consists of?
Set of parallel lines
Accumulators
Registers
None of the above
Which of the following is performed by half adder?
Binary addition operation for 2 decimal inputs
Binary addition operation for 2 binary inputs
Decimal addition operation for 2 decimal inputs
Binary addition operation for 2 binary inputs
Circuits that can hold their state as long as power is applied is ________.
Dynamic memory
Static memory
Register
Cache
The minimum time delay between two successive memory read operations is ________.
Cycle time
Latency
Delay
None of the mentioned
The drawback of building a large memory with DRAM is ________.
The large cost factor
The inefficient memory organization
The Slow speed of operation
All of the mentioned
The fastest data access is provided using ______
Caches
DRAM’s
SRAM’s
Registers
The next level of memory hierarchy after the L2 cache is ______
Secondary storage
TLB
Main memory
Register
The memory blocks are mapped on to the cache with the help of ______
Hash functions
Vectors
Mapping functions
None of the mentioned
During a write operation if the required block is not present in the cache then ______ occurs.
Write latency
Write hi
Write delay
Write miss
The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______
Set associative
Associative
Direct
Indirect
In ______ protocol the information is directly written into the main memory.
Write through
Write back
Write first
None of the mentioned
The benefit of using this approach is ______
It is cost effective
It is highly efficient
It is very reliable
It increases the speed of operation
The transfer of large chunks of data with the involvement of the processor is done by
DMA controller
Arbitrator
User system programs
None of the mentioned
The unit which acts as an intermediate agent between memory and backing store to reduce process time is
TLB’s
Registers
Page tables
Cache
The situation wherein the data of operands are not available is called ______
Data hazard
Stock
Deadlock
Structural hazard
The fetch and execution cycles are interleaved with the help of ______
Modification in processor architecture
Clock
Special unit
Control unit
The algorithm which replaces the block which has not been referenced for a while is called
LRU
ORF
Direct
Both LRU and ORF
The algorithm which removes the recently used page first is ______
LRU
MRU
OFM
None of the mentioned
In LRU, the referenced blocks counter is set to '0' and that of the previous blocks are incremented by one and others remain same, in the case of ______
Hit
Miss
Delay
None of the mentioned
In the case of, Zero-address instruction method the operands are stored in ______
Registers
Accumulators
Push down stack
Cache
The addressing mode which makes use of in-direction pointers is ______
Indirect addressing mode
Index addressing mode
Relative addressing mode
offset addressing mode
The addressing mode/s, which uses the PC instead of a general purpose register is ______
Indexed with offset
Relative
Direct
Both Indexed with offset and direct
The addressing mode, where you directly specify the operand value is ______
Immediate
Direct
Definite
Relative
The effective address of the following instruction is MUL 5(R1,R2).
5+R1+R2
5+(R1*R2)
5+[R1]+[R2]
5*([R1]+[R2])
In memory-mapped I/O ______
The I/O devices and the memory share the same address space
The I/O devices have a separate address space
The memory and I/O devices have an associated address space
A part of the memory is specifically set aside for the I/O operation
The usual BUS structure used to connect the I/O devices is _________
Star BUS structure
Multiple BUS structure
Single BUS structure
Node to Node BUS structure
The system is notified of a read or write operation by ______
Appending an extra bit of the address
Enabling the read or write bits of the devices
Raising an appropriate interrupt signal
Sending a special signal along the BUS
The method of accessing the I/O devices by repeatedly checking the status flags is ______
Program-controlled I/O
Memory-mapped I/O
I/O mapped
None of the mentioned
The method of synchronizing the processor with the I/O device in which the device sends a signal when it is ready is?
Exceptions
Signal handling
Interrupts
DMA
The method which offers higher speeds of I/O transfers is ______
interrupts
Memory mapping
Program-controlled I/O
DMA
In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______ bits.
24
23
20
16
The sign followed by the string of digits is called as ______
Significant
Determinant
Mantissa
Exponent
If the decimal point is placed to the right of the first significant digit, then the number is called ________
Orthogonal
Normalized
Determinate
None of the mentioned
In double precision format, the size of the mantissa is __________
32 bit
52 bit
64 bit
72 bit
We make use of ______ circuits to implement multiplication.
Flip flops
Combinatorial
Fast adders
None of the mentioned
The multiplier is stored in ______
PC Register
Shift register
Cache
None of the mentioned
The ______ is used to coordinate the operation of the multiplier.
Controller
Coordinator
Control sequencer
None of the mentioned
The multiplicand and the control signals are passed through to the n-bit adder via ______
MUX
DEMUX
Encoder
Decoder
The bits 1 & 1 are recorded as ______ in bit-pair recording.
-1
0
+1
both -1 and 0
CSA stands for?
Computer Speed Addition
Carry Save Addition
Computer Service Architecture
None of the mentioned
The computer architecture aimed at reducing the time of execution of instructions is ______
CISC
RISC
ISA
ANNA
Both the CISC and RISC architectures have been developed to reduce the ______
Cost
Time delay
Semantic gap
All of the mentioned
Which of the architecture is power efficient?
CISC
RISC
ISA
IANA
The ROM chips are mainly used to store ______
System files
Root directories
Boot files
Driver files
The disadvantage of the EPROM chip is
The high cost factor
The low efficiency
The low speed of operation
The need to remove the chip physically to reprogram it
In micro-programmed approach, the signals are generated by ______
Machine instructions
System programs
Utility tools
None of the mentioned
A sequence of control words corresponding to a control sequence is called ______
Micro routine
Micro function
Micro procedure
None of the mentioned
Individual control words of the micro routine are called as .
Micro task
Micro operation
Micro instruction
Micro command
Every time a new instruction is loaded into IR the output of ______ is loaded into UPC.
Starting address generator
Loader
Linker
Clock
The special memory used to store the micro routines of a computer is ________
Control table
Control store
Control mart
Control shop
The small extremely fast RAM is called as _______
Cache
Heaps
Accumulators
Stacks
To organize large memory chips we make use of __
Integrated chips
Upgraded hardware
Memory modules
None of the mentioned
The chip can be disabled or cut off from an external connection using ______
Chip select
LOCK
ACPT
RESET
The periods of time when the unit is idle is called as _____
Stalls
Bubbles
Hazards
Both Stalls and Bubbles
The contention for the usage of a hardware device is called
Structural hazard
Stalk
Deadlock
None of the mentioned
The stalling of the processor due to the unavailability of the instructions is called as
Control hazard
structural hazard
Input hazard
None of the mentioned
When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
The higher order byte of the word
The lower order byte of the word
Can't say
None of the mentioned
To get the physical address from the logical address generated by CPU we use ___________
MAR
MMU
Overlays
TLB
The smallest entity of memory is called _______
Cell
Block
Instance
Unit
The collection of the above mentioned entities where data is stored is called ______
Block
Set
Word
Byte
The type of memory assignment used in Intel processors is
Little Endian
Big Endian
Medium Endian
None of the mentioned
RTN stands for ____
Register Transfer Notation
Register Transmission Notation
Regular Transmission Notation
Regular Transfer Notation
The two phases of executing an instruction are __________
Instruction decoding and storage
Instruction fetch and instruction execution
Instruction execution and storage
Instruction fetch and Instruction processing
When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is called as
Branch target
Loop target
Forward target
Jump instruction
The condition flag Z is set to 1 to indicate ______
The operation has resulted in an error
The operation requires an interrupt call
The result is zero
There is no empty register available
The stack frame for each subroutine is present in _
Main memory
System Heap
Processor Stack
None of the mentioned
The main virtue for using single Bus structure is __________
Fast data transfers
Cost effective connectivity and speed
Cost effective connectivity and ease of attaching peripheral devices
None of the mention
are used to overcome the difference in data transfer speeds of various devices.
Speed enhancing circuitry
Bridge circuits
Multiple Buses
Buffer registers
The bus used to connect the monitor to the CPU is
PCI bus
SCSI bus
Memory bus
Rambus
In multiple bus organization, the registers are collectively placed and referred as
Set registers
Register file
Register Block
Map registers
The main advantage of multiple bus organization over a single bus is
Reduction in the number of cycles for execution
Increase in size of the registers
Better Connectivity
None of the mentioned
Write through technique is used in which memory for updating the data
Virtual Memory
Auxiliary memory
Main memory
Cache memory
The main memory in a personal computer is made of
Static RAM
Both c and d
Cache memory
Dynamic RAM
The operation executed on data stored in registers is called
Micro operation
Bit operation
macro operation
Byte operation
The time interval between adjacent bits is called the
Word time
Turnaround time
Bit time
slice time
