Transition time

Clock Uncertainty

Pulse width

Clock to output contamination delay (tccq)

As 1's complement

As unsigned binary

As 2's complement

As signed magnitude

tcd ≤ Tc − (tpcq + tsetup)

tcd ≥ thold − tccq

tcd ≤ tpcq + tsetup

tcd ≥ thold + tccq

Latency, Throughput, and Area

Performance (speed), Cost (complexity -area), and Power (energy dissipation)

Front-End Design, Back-End Design, and System Design

Boolean algebra, CMOS building blocks, and Logic gates

The output will be stable faster (low tpcq)

The clock may fail to trigger the intended state change

A hold violation is guaranteed

The clock skew increases

Using assign to drive a reg type

Using non-blocking assignments (<=) for combinational logic

When variable E depends on variable D, but D is also updated in the same cycle

When utilizing the parameter data type

Latency, Throughput, and Area

Performance (speed), Cost (complexity -area), and Power (energy dissipation)

Front -End Design, Back -End Design, and System Design

Boolean algebra, CMOS building blocks, and Logic gates

Code runs sequentially, similar to software

In HDL, the code blocks run in parallel

Verilog is purely sequential, but blocking assignments can introduce parallelism

Verilog is not case sensitive

The maximum delay caused by Clock Jitter

The difference between the required arrival time of a signal and its actual arrival time

The minimum time required for recovery from an asynchronous control signal

The difference between the maximum and minimum delay (Delay Spread)

Tc > tpd -max + tccq

Tc > tpcq -max + toverhead

Tc = tccq - thold

Tc = tpd − tcd

reg

integer

Nets (like wire)

Parameters

Only clock edges

Only reset signals

All signals being read

Only sequential elements

minimum time from input crossing 50% to output crossing 50% of amplitude

maximum time from input crossing 50% to output crossing 50% of amplitude

time interval between signal crossing 10% and 90% of VDD

total time taken for CL to change and data to appear at the next register

Full Custom

ASIC (Semi Custom) Design Flow

FPGA Design

Manual Transistor-level Design

tpd ≥ thold − tccq

tpd ≤ Tc − (tpcq + tsetup)

tpd ≥ thold + tccq

tpd ≤ tccq − thold

Extended by 0

Extended by 1

Extended by 0, X, or Z

Extended by 2's complement value

Physical View

Structural View

Behavioral View

Analog/Digital Integration

it treats only "X" as a do not care

it treats "Z" as a do not care

it treats both "Z" and "X" as do not cares

it is unsupported by synthesis

parallel_case

endcelldefine

unconnected_drive

full_case

after the clock edge where data must remain stable

before the clock edge where data must be stable

from the clock edge to the output contamination delay (tccq)

required for the signal to cross from 10% to 90% of VDD

a slight fluctuation in clock timing due to physical parameters

the difference in arrival times of the clock signal at different components or flip-flops

the time required for data to become stable after the clock edge

the maximum time from input crossing 50% to output crossing 50%

minimum time for FF input data to be stable before the clock edge

minimum time for FF input data to remain stable after the clock edge

minimum time for FF output to be stable after the active clock edge

maximum time from the input crossing 50% to the output crossing 50% of amplitude

minimum contamination delay

uniform periodicity

stable sequential elements

high removal time

must be purely combinational (=)

returns a value by its name

can have inputs, inouts, & outputs, and use both combinational (=) or sequential (<=) expressions

cannot be defined inside a module

Blocking assignments (=)

Continuous assignments (assign)

Non-blocking assignments (<=)

Conditional assignments

they evaluate R.H.Ss sequentially and update L.H.Ss immediately

they block all future assignments until the present assignment is evaluated

all R.H.Ss are evaluated at the same time, then L.H.Ss updated at the end of the time step

they force code to run sequentially, like software

Verilog Primitives

Logical Operators

Logic Value System

Procedural Assignment

improvement in critical path timing

immediate mismatch between simulation results and the gate -level netlist

assignment to be treated as non-blocking

better resource allocation

Continuous Assignment

Non-Blocking Assignment

Blocking Assignment

Conditional Assignment

Recovery Time

Removal Time

Setup Time

Propagation delay (tpd)

Negative

Zero

Positive

Equal to the Removal Time

Resource Allocation

Moving Code Outside Loops

Common Subexpressions/Common Factoring

Constant folding

It must use blocking assignments

It must be defined inside a named block

Its bounds must be constants

It must use a non -blocking assignment

Constant folding

Dead -code elimination

Resource Allocation (Resource Sharing)

Commutativity

Always Block

Procedural Assignment

Continuous Assignment

Module instantiation

8 bits

16 bits

32 bits

64 bits

Implementing module with built -in logic gates

Describing functionality at higher abstraction

Flow of data through combinational logic emphasizing direct input -output mapping

Instantiation of previously defined modules

shifts in the sign bit

shifts in LSB

fills evaluated bits with zeros

operates only on integers

Net

Register

Parameter

Supply0/Supply1

Only clock edges

Only reset signals

All signals being read

Only sequential elements

Redesign the circuit faster

Implement pipelining

Lower clock frequency

Insert buffers to increase delay

Setup time

Hold time

Propagation delay (tpd)

Clock to output contamination delay (tccq)

reg

integer

wire

parameter

inconsistent and different

the same

blocked until the end of simulation

updated immediately

Latency

Throughput

Area (cost ∝ area)

Clock speed

Inconsistent

Deterministic

Immediate update

Blocked until end of simulation

Clock Skew

Critical path

Setup time

Hold time

Continuous Assignment

Conditional Assignment

Blocking Assignment

Non -Blocking Assignment

reg

parameter

wire

integer

Clock Uncertainty

Clock Jitter

Clock Skew

Delay Spread

Extended by 0

Extended by 1

Extended by X

Extended by Z

Dead-code elimination

Common Factoring

Constant folding

Resource Allocation

Data arrival time is too late for the next clock edge

Data races through the combinational logic and violates the hold time of the receiving register

Clock skew exceeds clock uncertainty

The setup time is too large

Moving Code Outside Loops

Commutativity and Associativity

Common Subexpressions / Common Factoring

Dead-code elimination

It prevents Clock Jitter from affecting the inputs

It ensures inputs are stable during the entire clock cycle, even if they were ready beforehand

It fixes the Critical Path delay ( $$t_{pd}$$ ) to a constant value

It guarantees negative hold time

Behavioral modeling

Gate-level modeling

Data flow modeling

Structural modeling

function

parameter

task

always block

$$t_{pd}$$

$$t_{pcq} + t_{setup}$$

$$T_c$$

$$t_{setup}$$

It must be assigned under an edge-triggered condition

It must be assigned in all conditional branches

It must not be assigned in any conditional statement

It must be declared as a wire

The shortest path ( $$t_{cd}$$ )

The longest (critical) path ( $$t_{pd\_{max}}$$ )

The path determined by $$t_{ccq} - t_{hold}$$

The path defined by the Recovery Time

The use of wire types for output ports

The bounds of a for loop being constants

The evaluation order when a variable's dependent and independent values are updated in the same cycle

Using a casez statement instead of a standard case

Logic -1

High-impedance

Logic -0

Unknown

Identical, regardless of order

Inconsistent and different (Non-deterministic)

Immediately updated at the end of the simulation run

Only updated if R1 is listed in the sensitivity list

Pulse width

Clock Jitter

Transition time ( $$T_{rise}$$ / $$T_{fall}$$ )

Contamination delay ( $$t_{cd}$$ )

As signed magnitude

As 1's complement

As 2's complement

As an integer (32 bits)

Constant folding

Moving Code Outside Loops

Resource Sharing

Using a while loop instead

Contamination delay ( $$t_{cd}$$ )

Minimum Delay (Shortest Path)

Propagation delay ( $$t_{pd}$$ ) / Maximum Delay

Delay Spread ( $$\Delta t_{pd}$$ )

The signal is stable at an unknown value

The signal is high or low, but stable

The signal might change once or more over an interval of time

The signal is high impedance ('Z')

They force the synthesizer to use non-blocking assignments

They help identify common subexpressions and result in a shorter critical path

They ensure all arithmetic operations are treated as unsigned

They eliminate dead code

Hold Time constraint

Clock Jitter constraint

Setup Time constraint

Removal Time constraint

Behavioral modeling

Gate-level modeling

Data flow modeling

Structural modeling

Dead-code elimination

Resource Allocation / Resource Sharing

Constant folding

Common Subexpression

Asserted after the active clock edge

De-asserted before the active clock edge

Stable during the entire clock cycle

Allowed to fluctuate due to jitter

Lower clock frequency

Insert buffers to increase delay

Pipelining

Use a negative clock skew

Throughput

Fabrication Cost

Power Consumption

Latency

Data must change only after $$t_{ccq}$$

Data must remain stable until the next clock cycle

The data can change even before the clock edge

The data path has a minimum delay greater than zero

Simulation retains the previous value, while synthesis avoids the default latch

Simulation sets the unlisted case to 'X', while synthesis sets it to 'Z'

Synthesis always prioritizes the first matching branch

The missing case is automatically filled by the synthesizer with logic -0

Procedural Assignment

Continuous Assignment / Data Flow Modeling

Behavioral Modeling

Structural Modeling

wor and wand

reg and integer

wire and tri

supply0 and supply1

Clock to output propagation delay

Clock to output contamination delay

Setup time

Removal time

Forces non-blocking assignments

Identifies common subexpressions / shortens critical path

Forces unsigned arithmetic

Eliminates dead code

Hold Time violation

Clock Jitter violation

Setup Time violation

Removal Time violation

full_case

accelerate

nounconnected_drive

protect

Synthesis replaces them with standard == and != operators

Synthesis ignores them

They infer latches

Only valid for integers

Shifts in zeroes

Shifts in LSB

Shifts in the sign bit

Performs logical shift

Warning about unnecessary resource sharing

Warning about mixed assignments / non-deterministic behavior

Warning code runs sequentially

Warning about purely structural module

Only clock edge

All signals read (A, B, C)

Only reg variables

Only procedural blocks

Minimum time from input 50% → output 50%

Maximum time from input 50% → output 50%

Required stable time after clock edge

Minimum required clock pulse

Clock to output contamination delay

Minimum delay of critical path

Minimum cycle time $$T_{cs}$$ = $$t_{pd\text{-}max} + t_{overhead}$$

Minimum required recovery time

Wire

Latch

Flip-Flop

Combinational MUX

Logic optimizers cannot handle designs above threshold

Synthesis run times are exponential with size

Netlist will always fail STA

Only Full Custom flows support it

Contamination delay

Minimum delay

Propagation delay / maximum delay

Delay spread

Asserted after active clock edge

De-asserted before active clock edge

Stable during entire cycle

Allowed to fluctuate due to jitter

Lower clock frequency

Insert buffers to increase delay

Pipelining

Use negative clock skew

Throughput

Fabrication Cost

Power Consumption

Latency

Data must change only after $$t_{ccq}$$

Data must remain stable until next cycle

Data can change even before clock edge

Path has minimum delay > 0

Hold Time

Clock Jitter

Setup Time

Removal Time

$$t_{setup}$$ is related to t_pcq, t_hold to t_ccq

$$t_{setup}$$ stable before clock edge; $$t_{hold}$$ stable after

t_setup for async, t_hold for clock

t_setup prevents race-through, t_hold prevents critical path

t_pd

t_pcq + t_setup

T_c

t_setup

Non-blocking assignment (<=) should not be used for combinational logic

The sensitivity list is incomplete, as CK must also be included

GT should be declared as a wire, not a reg

Synthesis automatically converts CK to 'X'

Using the non-blocking assignment (<=)

Using only logic level sensitive inputs (e.g., always @(A or B))

An edge-triggered condition (e.g., posedge CLK)

Declaring the variable as an integer

The signal is stable at an unknown value

The signal might change once or more over an interval of time

The signal is stable, but its value is not important

The signal might change at that specific time

Eliminating variables that are not used

Calculating the value of constant expressions during compile time

Replacing $$R1 + R2$$ with $$SRUN$$

Moving code that is invariant with the loop index outside of the loop

$$t_{cs} < t_{pd\text{-}max}$$

A variable depends on another variable that is also being updated in the same cycle

Two continuous assignments target the same net

A conditional assignment uses the conditional operator ?

8 bits

16 bits

32 bits

64 bits

Required Time - Arrival Time

$$t_{pd\text{-}max} + t_{overhead}$$

$$t_{hold} - t_{ccq}$$

Arrival Time - Required Time

$$t_{pcq} + t_{setup}$$

$$t_{pd\text{-}max} + t_{ccq}$$

$$T_c - t_{pd\text{-}max}$$

$$t_{hold} - t_{ccq}$$

The critical path is too long, requiring a new layout

It signifies a race-through problem that cannot be fixed by lowering the clock frequency

It is a Setup violation, requiring faster devices

The pulse width of the clock is too short

Any operand is 32 bits wide

The comparison involves metalogical values like 'Z'

A bit value of any of the operands is 'X'

The assignment uses the assign keyword

Simulation runs sequentially, while synthesis executes branches in parallel

The conditions are treated as non-mutually exclusive in simulation

if-else logic is not supported by synthesis tools

It forces the use of blocking assignments

Recovery Time

Removal Time

Pulse Width constraint

Clock Jitter

The synthesizer will model the 5 time unit delay accurately

Synthesis will ignore the delay, causing mismatch

The delay will only be applied if $$C$$ is a register type

Synthesis will automatically compensate by using a faster gate implementation

A priority encoder

A Flip-Flop array

A Multiplexer (MUX)

A combinational logic path with maximum delay

Redesign for faster logic gates

Lower the clock frequency

Insert buffers to increase the delay

Implement pipelining

wire and tri

reg and integer

wor and wand

supply0 and supply1

6'b000011

6'b111100

6'b111101

32'b...1101

identical

inconsistent and different (non-deterministic)

Always updated at the end of the time step

Guaranteed to synthesize to a shared resource

Linear with design size

Constant for designs under 5000 gates

Exponential with design size

Only dependent on sequential elements

hold time equals setup time plus path delay

hold time is at least path contamination delay minus clock-to-output propagation

hold time is at most sum of path contamination delay and clock-to-output contamination

hold time is at most path propagation delay minus setup time

Shortest path contamination delay

Longest path propagation delay (max)

Delay spread (Δ propagation delay)

Setup slack

Use non‑blocking assignments

Reference variables defined outside the block

Be constants

Use the disable statement

Synthesis automatically converts them to == and !=

They infer a latch

They are reserved for integers

They cause synthesis runtime to become exponential

Use non‑blocking assignments

Include sequential logic and inputs

Be purely combinational and return a value by its name

Have non‑constant bounds

Using non‑blocking assignments

Assigned in a conditional statement

Needs to be saved between block invocations

Assigned in all branches of a conditional

1 ns

3 ns

4 ns

−1 ns

A=0, C=0

A=1, C=0

A=1, C=1

A=0, C=1

A=0, C=0

A=1, C=0

A=0, C=1

A=1, C=1

Synthesizes to a flip‑flop

Simulation mismatch due to unclear memory requirement

Synthesizer automatically infers a latch

Treated as a parameter

Fully supported

Supported if labeled

Not supported by synthesis

Automatically converted to parameter

Pulse width

Recovery time

Removal time

Clock skew

Contamination delay

Delay spread (Δ propagation delay)

Propagation delay

Clock jitter

Output appears one cycle delayed

Inputs remain stable during the entire clock cycle

Guarantee negative hold time

Eliminate clock skew

0.5 ns

0.7 ns

0.9 ns

−0.5 ns

Insert buffers

Lower the clock frequency

Make the logic faster or pipeline

Increase hold time

Priority encoder

Multiplexer selecting shared ALU outputs

Infers register type for shared variable

Constant folding

Behavioral (RTL)

Physical (layout)

Structural (netlist)

System design view

Changes type to signed

Helps synthesizer identify common subexpressions, shortening the critical path

Forces blocking assignments

Minimizes clock jitter

Resource allocation

Constant folding

Move code outside loops

Use conditional operator

Dead‑code elimination

Commutativity and associativity

Constant folding

Pipeline implementation

Pulse width

Recovery time

Removal time

Clock skew

Shortest path contamination delay

Longest path propagation delay (max)

Delay spread (Δ propagation delay)

Setup slack

Clock‑to‑output contamination delay (minimum time)

Time before clock edge where data must be stable

Time interval between 10%–90% VDD

Time difference in clock arrival

Signed

Unsigned

Two’s‑complement arithmetic

Saturated arithmetic

wire

tri

supply0

supply1

Synthesis sets missing branch to 'Z', simulation 'X'

Synthesis avoids latch inference, simulation retains previous value

Simulation treats as priority encoder

Synthesizer issues 'non-constant loop bound' error

Use non-blocking assignments

Include sequential logic and inouts

Be purely combinational and return a value

Have non-constant bounds

1 ns

3 ns

4 ns

-1 ns

A updates immediately, C uses the new value of A

Old values are used on RHS; new values update at the end of the timestep

Both A and C update at the same time using old values

Both A and C update at the same time using new values

Signed conversion

Detecting common subexpressions

Blocking assignments

Clock jitter reduction